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Searched refs:FPR (Results 1 – 25 of 33) sorted by relevance

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/external/valgrind/main/VEX/priv/
Dhost_s390_defs.c3271 s390_disasm(ENC3(MNM, FPR, FPR), "ldr", r1, r2); in s390_emit_LDR()
3281 s390_disasm(ENC3(MNM, FPR, UDXB), "le", r1, d2, x2, b2); in s390_emit_LE()
3291 s390_disasm(ENC3(MNM, FPR, UDXB), "ld", r1, d2, x2, b2); in s390_emit_LD()
3303 s390_disasm(ENC3(MNM, FPR, SDXB), "ley", r1, dh2, dl2, x2, b2); in s390_emit_LEY()
3315 s390_disasm(ENC3(MNM, FPR, SDXB), "ldy", r1, dh2, dl2, x2, b2); in s390_emit_LDY()
3337 s390_disasm(ENC3(MNM, FPR, GPR), "ldgr", r1, r2); in s390_emit_LDGR()
3349 s390_disasm(ENC3(MNM, GPR, FPR), "lgdr", r1, r2); in s390_emit_LGDR()
3359 s390_disasm(ENC2(MNM, FPR), "lzer", r1); in s390_emit_LZER()
3369 s390_disasm(ENC2(MNM, FPR), "lzdr", r1); in s390_emit_LZDR()
3389 s390_disasm(ENC3(MNM, FPR, UDXB), "ste", r1, d2, x2, b2); in s390_emit_STE()
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Dguest_s390_toIR.c1954 s390_disasm(ENC3(MNM, FPR, FPR), mnm, r1, r2); in s390_format_RR_FF()
1981 s390_disasm(ENC3(MNM, FPR, FPR), mnm, r1, r2); in s390_format_RRE_FF()
1991 s390_disasm(ENC3(MNM, GPR, FPR), mnm, r1, r2); in s390_format_RRE_RF()
2001 s390_disasm(ENC3(MNM, FPR, GPR), mnm, r1, r2); in s390_format_RRE_FR()
2021 s390_disasm(ENC2(MNM, FPR), mnm, r1); in s390_format_RRE_F0()
2041 s390_disasm(ENC4(MNM, FPR, FPR, FPR), mnm, r1, r3, r2); in s390_format_RRF_F0FF()
2051 s390_disasm(ENC4(MNM, FPR, FPR, GPR), mnm, r1, r3, r2); in s390_format_RRF_F0FR()
2062 s390_disasm(ENC5(MNM, FPR, UINT, FPR, UINT), mnm, r1, m3, r2, m4); in s390_format_RRF_UUFF()
2072 s390_disasm(ENC4(MNM, FPR, FPR, UINT), mnm, r1, r2, m4); in s390_format_RRF_0UFF()
2083 s390_disasm(ENC5(MNM, FPR, UINT, GPR, UINT), mnm, r1, m3, r2, m4); in s390_format_RRF_UUFR()
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/external/llvm/lib/Target/SystemZ/
DSystemZMachineFunctionInfo.h49 void setVarArgsFirstFPR(unsigned FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR() argument
DSystemZRegisterInfo.td122 // Maps FPR register numbers to their DWARF encoding.
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td47 // FPR - One of the 32 64-bit floating-point registers
48 class FPR<bits<5> num, string n> : PPCReg<n> {
69 class VSRL<FPR SubReg, string n> : PPCReg<n> {
108 def F#Index : FPR<Index, "f"#Index>,
125 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
126 DwarfRegAlias<!cast<FPR>("F"#Index)>;
DPPCISelLowering.cpp2115 static const MCPhysReg FPR[] = { in GetFPR() local
2120 return FPR; in GetFPR()
2459 static const MCPhysReg *FPR = GetFPR(); in LowerFormalArguments_64SVR4() local
2615 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); in LowerFormalArguments_64SVR4()
2617 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ? in LowerFormalArguments_64SVR4()
2740 static const MCPhysReg *FPR = GetFPR(); in LowerFormalArguments_Darwin() local
2956 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); in LowerFormalArguments_Darwin()
2958 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); in LowerFormalArguments_Darwin()
4037 static const MCPhysReg *FPR = GetFPR(); in LowerCall_64SVR4() local
4214 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); in LowerCall_64SVR4()
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/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
167 [!cast<FPR>("F"#!shl(I, 1)),
168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
/external/lldb/source/Plugins/Process/POSIX/
DRegisterContext_x86_64.h303 struct FPR struct
329 … FPR m_fpr; // floating-point registers including extended register sets.
DRegisterContext_x86_64.cpp294 (offsetof(RegisterContext_x86_64::FPR, xstate) + \
355 #define REG_CONTEXT_SIZE (GetGPRSize() + sizeof(RegisterContext_x86_64::FPR))
501 ::memset(&m_fpr, 0, sizeof(RegisterContext_x86_64::FPR)); in RegisterContext_x86_64()
/external/llvm/test/CodeGen/AArch64/
Darm64-fixed-point-scalar-cvt-dagcombine.ll5 ; of the value to a GPR and back to and FPR.
Darm64-scvt.ll58 ; GPR -> FPR.
/external/llvm/test/CodeGen/SystemZ/
Dasm-10.ll1 ; Test the FPR constraint "f".
Dframe-04.ll68 ; Like f1, but requires one fewer FPR pair. We allocate in numerical order,
121 ; Like f1, but requires only one call-saved FPR pair. We allocate in
Dargs-02.ll1 ; Test the handling of GPR, FPR and stack arguments when integers are
Dargs-03.ll1 ; Test the handling of GPR, FPR and stack arguments when integers are
Dargs-01.ll1 ; Test the handling of GPR, FPR and stack arguments when no extension
Dframe-02.ll91 ; Like f1, but requires one fewer FPR. We allocate in numerical order,
170 ; Like f1, but should require only one call-saved FPR.
Dframe-03.ll93 ; Like f1, but requires one fewer FPR. We allocate in numerical order,
172 ; Like f1, but should require only one call-saved FPR.
Dargs-04.ll1 ; Test incoming GPR, FPR and stack arguments when no extension type is given.
Dfp-move-02.ll12 ; 32 bits of the FPR.
80 ; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
Dframe-07.ll9 ; as well as the 8 FPR save slots. Get a frame of size 4128 by allocating
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td44 // up to eight each of GPR and FPR.
119 // up to eight each of GPR and FPR.
DAArch64InstrInfo.td1802 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1804 def : Pat<(store (VecTy FPR:$Rt),
1806 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1808 def : Pat<(store (VecTy FPR:$Rt),
1810 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
4442 // SCVTF GPR -> FPR is 9 cycles.
4443 // SCVTF FPR -> FPR is 4 cyclces.
4444 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4445 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
DAArch64InstrFormats.td3525 let Inst{22} = 0; // 32-bit FPR flag
3530 let Inst{22} = 1; // 64-bit FPR flag
3535 let Inst{22} = 0; // 32-bit FPR flag
3540 let Inst{22} = 1; // 64-bit FPR flag
3549 let Inst{22} = 0; // 32-bit FPR flag
3558 let Inst{22} = 1; // 64-bit FPR flag
3567 let Inst{22} = 0; // 32-bit FPR flag
3575 let Inst{22} = 1; // 64-bit FPR flag
3651 let Inst{22} = 0; // 32-bit FPR flag
3656 let Inst{22} = 1; // 64-bit FPR flag
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DAArch64SchedCyclone.td328 // Move FPR is a register rename and single nop micro-op.

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