Searched refs:FirstReg (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 265 unsigned FirstReg = 0; in CreateRegs() local
273 if (!FirstReg) FirstReg = R; in CreateRegs()
276 return FirstReg; in CreateRegs()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 484 unsigned FirstReg = 0; in ScanInstruction() local
491 if (FirstReg != 0) { in ScanInstruction()
493 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
496 FirstReg = Reg; in ScanInstruction()
500 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 667 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
673 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
674 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
676 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
678 unsigned OldFirstReg = FirstReg; in insertSelect()
679 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
680 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
685 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1174 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1175 Reg = FirstReg; in printVectorList()
1176 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1177 Reg = FirstReg; in printVectorList()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1163 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList64Operands() local
1166 MCOperand::CreateReg(FirstReg + getVectorListStart() - AArch64::Q0)); in addVectorList64Operands()
1174 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList128Operands() local
1177 MCOperand::CreateReg(FirstReg + getVectorListStart() - AArch64::Q0)); in addVectorList128Operands()
2832 int64_t FirstReg = tryMatchVectorRegister(Kind, true); in parseVectorList() local
2833 if (FirstReg == -1) in parseVectorList()
2835 int64_t PrevReg = FirstReg; in parseVectorList()
2894 FirstReg, Count, NumElements, ElementKind, S, getLoc(), getContext())); in parseVectorList()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3541 unsigned FirstReg = Reg; in parseVectorList() local
3545 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
3687 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
3690 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, in parseVectorList()
3700 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
3702 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, in parseVectorList()
3707 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 1923 unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); in tryFoldSPUpdateIntoPushPop() local
1944 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded; in tryFoldSPUpdateIntoPushPop()
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