Searched refs:GPRC (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 304 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
305 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
354 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
362 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
402 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
404 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
416 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
446 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore() local
448 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
460 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
[all …]
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| D | PPCRegisterInfo.td | 228 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
239 def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>;
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| D | PPCFrameLowering.cpp | 1338 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in addScavengingSpillSlot() local
1340 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
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| D | PPCInstrInfo.td | 360 def gprc : RegisterOperand<GPRC> {
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | asym-regclass-copy.ll | 5 ; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with
6 ; GPRC is handled correctly. When it was not, this test would assert.
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| /external/llvm/docs/ |
| D | CodeGenerator.rst | 1061 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
1065 def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
1066 (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;
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