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Searched refs:IsShiftedRegister (Results 1 – 7 of 7) sorted by relevance

/external/chromium_org/v8/src/arm64/
Dassembler-arm64-inl.h370 bool Operand::IsShiftedRegister() const {
390 ASSERT(IsShiftedRegister());
409 ASSERT(IsShiftedRegister() || IsExtendedRegister());
415 ASSERT(IsShiftedRegister());
427 ASSERT(IsShiftedRegister() || IsExtendedRegister());
498 } else if (offset.IsShiftedRegister()) {
Dassembler-arm64.cc1925 } else if (operand.IsShiftedRegister()) { in AddSub()
1957 ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0)); in AddSubWithCarry()
2038 ASSERT(operand.IsShiftedRegister()); in Logical()
2072 ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0)); in ConditionalCompare()
2179 ASSERT(operand.IsShiftedRegister()); in DataProcShiftedRegister()
Dmacro-assembler-arm64.cc147 ASSERT(operand.IsShiftedRegister()); in LogicalMacro()
259 } else if (operand.IsShiftedRegister() && (operand.shift_amount() != 0)) { in Mov()
361 } else if ((operand.IsShiftedRegister() && (operand.shift_amount() == 0)) || in ConditionalCompareMacro()
403 } else if (operand.IsShiftedRegister() && (operand.shift_amount() == 0)) { in Csel()
434 (rn.IsZero() && !operand.IsShiftedRegister()) || in AddSubMacro()
435 (operand.IsShiftedRegister() && (operand.shift() == ROR))) { in AddSubMacro()
460 (operand.IsShiftedRegister() && (operand.shift() == ROR))) { in AddSubWithCarryMacro()
466 } else if (operand.IsShiftedRegister() && (operand.shift_amount() != 0)) { in AddSubWithCarryMacro()
Dassembler-arm64.h666 inline bool IsShiftedRegister() const;
/external/vixl/src/a64/
Dmacro-assembler-a64.cc208 VIXL_ASSERT(operand.IsShiftedRegister()); in LogicalMacro()
221 } else if (operand.IsShiftedRegister() && (operand.shift_amount() != 0)) { in Mov()
418 if ((operand.IsShiftedRegister() && (operand.shift_amount() == 0)) || in ConditionalCompareMacro()
459 } else if (operand.IsShiftedRegister() && (operand.shift_amount() == 0)) { in Csel()
612 (rn.IsZero() && !operand.IsShiftedRegister()) || in AddSubMacro()
613 (operand.IsShiftedRegister() && (operand.shift() == ROR))) { in AddSubMacro()
681 (operand.IsShiftedRegister() && (operand.shift() == ROR))) { in AddSubWithCarryMacro()
686 } else if (operand.IsShiftedRegister() && (operand.shift_amount() != 0)) { in AddSubWithCarryMacro()
Dassembler-a64.cc244 bool Operand::IsShiftedRegister() const { in IsShiftedRegister() function in vixl::Operand
264 VIXL_ASSERT(IsShiftedRegister()); in ToExtendedRegister()
310 } else if (offset.IsShiftedRegister()) { in MemOperand()
1595 } else if (operand.IsShiftedRegister()) { in AddSub()
1627 VIXL_ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0)); in AddSubWithCarry()
1672 VIXL_ASSERT(operand.IsShiftedRegister()); in Logical()
1705 VIXL_ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0)); in ConditionalCompare()
1812 VIXL_ASSERT(operand.IsShiftedRegister()); in DataProcShiftedRegister()
Dassembler-a64.h492 bool IsShiftedRegister() const;
506 VIXL_ASSERT(IsShiftedRegister() || IsExtendedRegister()); in reg()
511 VIXL_ASSERT(IsShiftedRegister()); in shift()
521 VIXL_ASSERT(IsShiftedRegister() || IsExtendedRegister()); in shift_amount()