| /external/llvm/test/Transforms/LoopStrengthReduce/ARM/ |
| D | 2012-06-15-lsr-noaddrmode.ll | 3 ; LSR should only check for valid address modes when the IV user is a
11 ; LSR before the fix:
13 ; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
15 ; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32
17 ; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
19 ; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
21 ; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
24 ; LSR after the fix:
26 ; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
28 ; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32
[all …]
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| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_420p.s | 147 MOV r9,r9,LSR #1 @// height/2
148 @ MOV r8,r8,LSR #1 @// Width/2
151 MOV r11,r8,LSR #1
184 SUB r3,r3,r6,LSR #1
185 SUB r5,r5,r6,LSR #1
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| D | ihevcd_fmt_conv_420sp_to_420sp.s | 151 MOV r9,r9,LSR #1 @// height/2
152 @ MOV r8,r8,LSR #1 @// Width/2
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| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 144 @, LSR #1 @// u offset
145 @SUB R12,R8,R3, LSR #1 @// v offset
149 MOV R5,R5, LSR #1 @// height_cnt = height / 16
162 MOV R6,R3, LSR #4 @// width_cnt = width / 16
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| /external/libhevc/decoder/arm64/ |
| D | ihevcd_fmt_conv_420sp_to_420p.s | 148 LSR x9, x9, #1 //// height/2
152 LSR x11, x8, #1
187 SUB x3,x3,x6,LSR #1
188 SUB x5,x5,x6,LSR #1
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| /external/llvm/test/Transforms/LoopStrengthReduce/X86/ |
| D | 2011-11-29-postincphi.ll | 4 ; LSR first expands %t3 to %t2 in %phi
5 ; LSR then expands %t2 in %phi into two decrements, one on each loop exit.
12 ; Check that LSR did something close to the behavior at the time of the bug.
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| D | 2011-07-20-DoubleIV.ll | 3 ; Test LSR's OptimizeShadowIV. Handle a floating-point IV with a
7 ; First, make sure LSR doesn't crash on an empty IVUsers list.
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| D | 2011-12-04-loserreg.ll | 3 ; Test LSR's ability to prune formulae that refer to nonexistent
6 ; Unable to reduce this case further because it requires LSR to exceed
9 ; We really just want to ensure that LSR can process this loop without
12 ; verify that LSR removes it.
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| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| D | 2012-01-02-nopreheader.ll | 9 ; LSR should convert the inner loop (bb7.us) IV (j.01.us) into float*.
13 ; Currently, LSR won't kick in on such loops.
55 ; that LSR picks. We must detect that %bb8.preheader does not have a
56 ; preheader and avoid performing LSR on %bb7.
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| D | phi_node_update_multiple_preds.ll | 2 ; LSR should not crash on this.
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| /external/tremolo/Tremolo/ |
| D | dpen.s | 99 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
124 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
143 LDRB r14,[r12,r14,LSR #7] @ r14= t[chase+bit+1+(!bit || t[chase]0x0x80)]
154 MOV r6, r6, LSR #1
156 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
181 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
201 ADC r12,r8, r14,LSR #15 @ r12= 1+((chase+bit)<<1)+(!bit || t[chase]0x0x8000)
202 ADC r12,r12,r14,LSR #15 @ r12= t + (1+chase+bit+(!bit || t[chase]0x0x8000))<<1
214 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
299 MOV r8, r8, LSR r2 @ r8 = entry>>s->q_bits
[all …]
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| D | bitwiseARM.s | 57 MOV r10,r10,LSR r14 @ r10= ptr[0]>>(32-bitsLeftInWord)
81 MOV r10,r10,LSR r14 @ r10= first bitsLeftInWord bits
155 ADD r6,r10,r10,LSR #3 @ r6 = pointer to data
248 MOV r10,r10,LSR r14 @ r10= ptr[0]>>(32-bitsLeftInWord)
273 MOV r10,r10,LSR r14 @ r10= first bitsLeftInWord bits
395 ADD r6,r10,r10,LSR #3 @ r6 = pointer to data
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| /external/linux-tools-perf/perf-3.12.0/arch/metag/lib/ |
| D | memcpy.S | 53 LSR D1Ar5, D1Ar3, #3 ! D1Ar5 = number of 8 byte blocks
120 LSR D0Re0, D0Re0, D0Ar6
125 LSR D0Ar2, D0Ar2, D0Ar6
145 LSR D0Re0, D0Re0, D0Ar6
149 LSR D0FrT, D0Ar2, D0Ar6
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| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| D | armSP_FFT_CToC_FC32_Radix2_unsafe_s.S | 93 LSR subFFTNum,subFFTNum,#1 @//grpSize
117 MOV setCount,pointStep,LSR #3
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| D | armSP_FFT_CToC_SC16_Radix2_unsafe_s.S | 99 LSR subFFTNum,subFFTNum,#1 @//grpSize
124 MOV setCount,pointStep,LSR #2
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| D | armSP_FFT_CToC_SC32_Radix2_unsafe_s.S | 101 LSR subFFTNum,subFFTNum,#1 @//grpSize
124 MOV setCount,pointStep,LSR #3
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| D | armSP_FFT_CToC_FC32_Radix2_fs_unsafe_s.S | 85 LSR grpSize,subFFTNum,#1
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| D | armSP_FFT_CToC_SC32_Radix2_fs_unsafe_s.S | 93 LSR grpSize,subFFTNum,#1
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| D | armSP_FFT_CToC_SC16_Radix2_fs_unsafe_s.S | 97 LSR grpSize,subFFTNum,#1
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 35 LSR, enumerator
56 case AArch64_AM::LSR: return "lsr"; in getShiftExtendName()
77 case 1: return AArch64_AM::LSR; in getShiftType()
105 case AArch64_AM::LSR: STEnc = 1; break; in getShifterImm()
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| /external/llvm/test/CodeGen/X86/ |
| D | negative-stride-fptosi-user.ll | 3 ; LSR previously eliminated the sitofp by introducing an induction
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| D | loop-hoist.ll | 1 ; LSR should hoist the load from the "Arr" stub out of the loop.
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| D | lsr-nonaffine.ll | 3 ; LSR should leave non-affine expressions alone because it currently
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| D | optimize-max-2.ll | 7 ; LSR's OptimizeMax function shouldn't try to eliminate this max, because
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| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| D | armSP_FFT_CToC_FC32_Radix2_fs_s.S | 87 LSR grpSize,subFFTNum,#1
|