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Searched refs:M0 (Results 1 – 25 of 57) sorted by relevance

123

/external/chromium_org/third_party/mesa/src/src/mesa/sparc/
Dsparc_matrix.h35 #define M0 %f16 macro
53 ldd [BASE + ( 0 * 0x4)], M0; \
59 ldd [BASE + ( 0 * 0x4)], M0; \
63 ld [BASE + ( 0 * 0x4)], M0; \
67 ldd [BASE + ( 0 * 0x4)], M0; \
73 ld [BASE + ( 0 * 0x4)], M0; \
78 ld [BASE + ( 0 * 0x4)], M0; \
82 ldd [BASE + ( 0 * 0x4)], M0; \
90 ld [BASE + ( 0 * 0x4)], M0; \
95 ldd [BASE + ( 0 * 0x4)], M0; \
[all …]
Dxform.S82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
86 fmuls %f8, M0, %f9 ! FGM Group f1 available
115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
197 fmuls %f0, M0, %f1 ! FGM Group
199 fmuls %f8, M0, %f9 ! FGM Group
218 fmuls %f0, M0, %f1
251 fmuls %f0, M0, %f1 ! FGM Group
252 fmuls %f4, M0, %f5 ! FGM Group
268 fmuls %f0, M0, %f1
299 fmuls %f0, M0, %f1 ! FGM Group
[all …]
Dnorm.S60 fmuls %f0, M0, %f3 ! FGM Group
104 fmuls M0, %f15, M0
125 fmuls %f0, M0, %f3 ! FGM Group
199 fmuls %f0, M0, %f3 ! FGM Group
231 fmuls M0, %f15, M0
246 fmuls %f0, M0, %f3 ! FGM Group
291 fmuls M0, %f15, M0
305 fmuls %f0, M0, %f3 ! FGM Group
342 fmuls M0, %f15, M0
358 fmuls %f0, M0, %f3 ! FGM Group
[all …]
/external/mesa3d/src/mesa/sparc/
Dsparc_matrix.h35 #define M0 %f16 macro
53 ldd [BASE + ( 0 * 0x4)], M0; \
59 ldd [BASE + ( 0 * 0x4)], M0; \
63 ld [BASE + ( 0 * 0x4)], M0; \
67 ldd [BASE + ( 0 * 0x4)], M0; \
73 ld [BASE + ( 0 * 0x4)], M0; \
78 ld [BASE + ( 0 * 0x4)], M0; \
82 ldd [BASE + ( 0 * 0x4)], M0; \
90 ld [BASE + ( 0 * 0x4)], M0; \
95 ldd [BASE + ( 0 * 0x4)], M0; \
[all …]
Dxform.S82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
86 fmuls %f8, M0, %f9 ! FGM Group f1 available
115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
197 fmuls %f0, M0, %f1 ! FGM Group
199 fmuls %f8, M0, %f9 ! FGM Group
218 fmuls %f0, M0, %f1
251 fmuls %f0, M0, %f1 ! FGM Group
252 fmuls %f4, M0, %f5 ! FGM Group
268 fmuls %f0, M0, %f1
299 fmuls %f0, M0, %f1 ! FGM Group
[all …]
Dnorm.S60 fmuls %f0, M0, %f3 ! FGM Group
104 fmuls M0, %f15, M0
125 fmuls %f0, M0, %f3 ! FGM Group
199 fmuls %f0, M0, %f3 ! FGM Group
231 fmuls M0, %f15, M0
246 fmuls %f0, M0, %f3 ! FGM Group
291 fmuls M0, %f15, M0
305 fmuls %f0, M0, %f3 ! FGM Group
342 fmuls M0, %f15, M0
358 fmuls %f0, M0, %f3 ! FGM Group
[all …]
/external/chromium_org/ui/events/gestures/
Dgestures.dot22 GS_PENDING_SYNTHETIC_CLICK -> GS_SCROLL [label= "M0\n S0"];
23 GS_PENDING_SYNTHETIC_CLICK -> GS_PENDING_SYNTHETIC_CLICK [label= "M0\n S0"];
25 GS_PENDING_SYNTHETIC_CLICK -> GS_PENDING_SYNTHETIC_CLICK_NO_SCROLL [label= "M0"];
28 GS_PENDING_SYNTHETIC_CLICK -> GS_SYNTHETIC_CLICK_ABORTED [label= "M0"];
30 GS_PENDING_SYNTHETIC_CLICK_NO_SCROLL -> GS_PENDING_SYNTHETIC_CLICK_NO_SCROLL [label= "M0\n S0"];
34 GS_PENDING_SYNTHETIC_CLICK_NO_SCROLL -> GS_SYNTHETIC_CLICK_ABORTED [label= "M0"];
39 GS_SCROLL -> GS_SCROLL [label= "M0"];
43 GS_PENDING_PINCH -> GS_PENDING_PINCH [label= "M0\n M1"];
44 GS_PENDING_PINCH -> GS_PENDING_PINCH_NO_PINCH [label= "M0\n M1"];
45 GS_PENDING_PINCH -> GS_PINCH [label= "M0\n M1"];
[all …]
/external/llvm/test/CodeGen/R600/
Dlocal-64.ll4 ; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x1c, [M0]
14 ; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x0, [M0]
24 ; SI: DS_READ_U8 [[REG:v[0-9]+]], {{v[0-9]+}}, 0xffff, [M0]
36 ; SI: DS_READ_U8 [[REG:v[0-9]+]], [[VREGADDR]], 0x0, [M0]
47 ; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
57 ; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
67 ; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
77 ; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
87 ; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
96 ; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
[all …]
Datomic_cmp_swap_local.ll9 ; SI: DS_CMPST_RTN_B32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]], 0x10, [M0]
28 …]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}}, 0x20, [M0]
/external/llvm/include/llvm/Support/
DCommandLine.h1210 explicit opt(const M0t &M0) : Option(Optional, NotHidden) {
1211 apply(M0, this);
1217 opt(const M0t &M0, const M1t &M1) : Option(Optional, NotHidden) {
1218 apply(M0, this); apply(M1, this);
1224 opt(const M0t &M0, const M1t &M1,
1226 apply(M0, this); apply(M1, this); apply(M2, this);
1231 opt(const M0t &M0, const M1t &M1, const M2t &M2,
1233 apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
1238 opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,
1240 apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
[all …]
/external/llvm/unittests/Support/
DCommandLineTest.cpp51 explicit StackOption(const M0t &M0) : Base(M0) {} in StackOption() argument
55 StackOption(const M0t &M0, const M1t &M1) : Base(M0, M1) {} in StackOption() argument
59 StackOption(const M0t &M0, const M1t &M1, const M2t &M2) : Base(M0, M1, M2) {} in StackOption() argument
63 StackOption(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3) in StackOption() argument
64 : Base(M0, M1, M2, M3) {} in StackOption()
/external/openssl/crypto/md5/asm/
Dmd5-ia64.S125 #define M0 in4 macro
542 G(A, B, C, D, M0) \
543 COMPUTE(A, B, 5, M0, RotateM0) \
552 H(A, B, C, D, M0) \
553 COMPUTE(A, B, 4, M0, RotateM0) \
562 I(A, B, C, D, M0) \
563 COMPUTE(A, B, 6, M0, RotateM0) \
666 mov Z = M0
677 mov M0 = M1
719 mov Z = M0
[all …]
/external/chromium_org/third_party/openssl/openssl/crypto/md5/asm/
Dmd5-ia64.S125 #define M0 in4 macro
542 G(A, B, C, D, M0) \
543 COMPUTE(A, B, 5, M0, RotateM0) \
552 H(A, B, C, D, M0) \
553 COMPUTE(A, B, 4, M0, RotateM0) \
562 I(A, B, C, D, M0) \
563 COMPUTE(A, B, 6, M0, RotateM0) \
666 mov Z = M0
677 mov M0 = M1
719 mov Z = M0
[all …]
/external/llvm/test/CodeGen/ARM/
Dbuild-attributes.ll25 …N: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
345 ; CORTEX-M0: .cpu cortex-m0
346 ; CORTEX-M0: .eabi_attribute 6, 12
347 ; CORTEX-M0-NOT: .eabi_attribute 7
348 ; CORTEX-M0: .eabi_attribute 8, 0
349 ; CORTEX-M0: .eabi_attribute 9, 1
350 ; CORTEX-M0: .eabi_attribute 24, 1
351 ; CORTEX-M0: .eabi_attribute 25, 1
352 ; CORTEX-M0-NOT: .eabi_attribute 27
353 ; CORTEX-M0-NOT: .eabi_attribute 28
[all …]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DSIISelLowering.cpp153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); in LowerSI_INTERP() local
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP()
168 .addReg(M0); in LowerSI_INTERP()
176 .addReg(M0); in LowerSI_INTERP()
189 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); in LowerSI_INTERP_CONST() local
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP_CONST()
198 .addReg(M0); in LowerSI_INTERP_CONST()
DSIRegisterInfo.cpp36 case AMDGPU::M0: return 124; in getBinaryCode()
/external/mesa3d/src/gallium/drivers/radeon/
DSIISelLowering.cpp153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); in LowerSI_INTERP() local
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP()
168 .addReg(M0); in LowerSI_INTERP()
176 .addReg(M0); in LowerSI_INTERP()
189 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); in LowerSI_INTERP_CONST() local
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP_CONST()
198 .addReg(M0); in LowerSI_INTERP_CONST()
DSIRegisterInfo.cpp36 case AMDGPU::M0: return 124; in getBinaryCode()
/external/llvm/lib/Target/R600/
DSILowerControlFlow.cpp329 AMDGPU::M0).addImm(0xffffffff); in InitM0ForLDS()
342 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in LoadM0()
360 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in LoadM0()
365 .addReg(AMDGPU::M0) in LoadM0()
414 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectSrc()
436 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectDst()
DSIRegisterInfo.td32 def M0 : SIReg <"M0", 124>;
154 // Special register classes for predicates and the M0 register
158 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
/external/chromium_org/third_party/openssl/openssl/crypto/poly1305/
Dpoly1305_vec.c333 xmmi M0,M1,M2,M3,M4; in poly1305_blocks() local
367 M0 = _mm_and_si128(MMASK, T5); in poly1305_blocks()
375 …T5 = _mm_mul_epu32(M0, p->R20.v); T6 = _mm_mul_epu32(M0, p->R21.v); T0 = _mm_add_epi64(T0, T5); T1… in poly1305_blocks()
380 …T5 = _mm_mul_epu32(M0, p->R22.v); T6 = _mm_mul_epu32(M0, p->R23.v); T2 = _mm_add_epi64(T2, T5); T3… in poly1305_blocks()
385 T5 = _mm_mul_epu32(M0, p->R24.v); T4 = _mm_add_epi64(T4, T5); in poly1305_blocks()
394 M0 = _mm_and_si128(MMASK, T5); in poly1305_blocks()
401 T0 = _mm_add_epi64(T0, M0); in poly1305_blocks()
441 xmmi M0,M1,M2,M3,M4; in poly1305_combine() local
483 M0 = _mm_and_si128(MMASK, T5); in poly1305_combine()
490 T0 = _mm_add_epi64(T0, M0); in poly1305_combine()
/external/openssl/crypto/bn/asm/
Darmv4-mont.pl251 my ($Bi,$Ni,$M0)=map("d$_",(28..31));
275 vld1.32 {${M0}[0]}, [$n0,:32]
289 vmul.u32 $Ni,$temp,$M0
343 vmul.u32 $Ni,$temp,$M0
468 vmul.u32 $Ni,$temp,$M0
/external/llvm/test/CodeGen/Thumb/
D2012-04-26-M0ISelBug.ll2 ; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
/external/llvm/unittests/Analysis/
DScalarEvolutionTest.cpp64 const SCEVMulExpr *M0 = cast<SCEVMulExpr>(P0); in TEST_F() local
68 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(), in TEST_F()
76 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F()
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F()
/external/opencv/cvaux/src/
Dcvbgfg_codebook.cpp238 uchar m0, m1, m2, M0, M1, M2; in cvBGCodeBookDiff() local
256 m0 = model->modMin[0]; M0 = model->modMax[0]; in cvBGCodeBookDiff()
272 int h0 = p0 - M0, h1 = p1 - M1, h2 = p2 - M2; in cvBGCodeBookDiff()

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