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Searched refs:MIB (Results 1 – 25 of 62) sorted by relevance

123

/external/llvm/lib/Target/X86/
DX86InstrBuilder.h91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
99 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
108 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
115 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
123 addFullAddress(const MachineInstrBuilder &MIB, in addFullAddress() argument
128 MIB.addReg(AM.Base.Reg); in addFullAddress()
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DX86InstrInfo.cpp1972 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), in convertToThreeAddressWithLEA() local
1978 MIB.addReg(0).addImm(1 << ShAmt) in convertToThreeAddressWithLEA()
1984 addRegOffset(MIB, leaInReg, true, 1); in convertToThreeAddressWithLEA()
1988 addRegOffset(MIB, leaInReg, true, -1); in convertToThreeAddressWithLEA()
1994 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); in convertToThreeAddressWithLEA()
2005 addRegReg(MIB, leaInReg, true, leaInReg, false); in convertToThreeAddressWithLEA()
2013 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); in convertToThreeAddressWithLEA()
2015 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) in convertToThreeAddressWithLEA()
2018 addRegReg(MIB, leaInReg, true, leaInReg2, true); in convertToThreeAddressWithLEA()
2026 MachineInstr *NewMI = MIB; in convertToThreeAddressWithLEA()
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/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp207 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
240 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
253 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
265 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
307 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
320 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
352 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
354 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
355 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
362 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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DInstrEmitter.h53 MachineInstrBuilder &MIB,
66 void AddRegisterOperand(MachineInstrBuilder &MIB,
77 void AddOperand(MachineInstrBuilder &MIB,
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp389 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
397 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
399 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
401 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
403 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
406 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
409 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
410 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
413 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
423 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
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DThumb1RegisterInfo.cpp128 MachineInstrBuilder MIB = in emitThumbRegPlusImmInReg() local
131 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmInReg()
133 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
135 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
136 AddDefaultPred(MIB); in emitThumbRegPlusImmInReg()
240 const MachineInstrBuilder MIB = in emitThumbRegPlusImmediate() local
243 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); in emitThumbRegPlusImmediate()
259 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmediate() local
261 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmediate()
262 MIB.addReg(DestReg).addImm(ThisVal); in emitThumbRegPlusImmediate()
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DThumb2SizeReduction.cpp494 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore() local
496 MIB.addOperand(MI->getOperand(0)); in ReduceLoadStore()
497 MIB.addOperand(MI->getOperand(1)); in ReduceLoadStore()
500 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
505 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); in ReduceLoadStore()
510 MIB.addOperand(MI->getOperand(OpNum)); in ReduceLoadStore()
513 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in ReduceLoadStore()
516 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore()
518 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); in ReduceLoadStore()
554 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), in ReduceSpecial() local
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DARMBaseInstrInfo.cpp691 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg() local
692 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
694 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
695 AddDefaultPred(MIB); in copyPhysReg()
784 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, in AddDReg() argument
788 return MIB.addReg(Reg, State); in AddDReg()
791 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); in AddDReg()
792 return MIB.addReg(Reg, State, SubIdx); in AddDReg()
832 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); in storeRegToStackSlot() local
833 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
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DThumb1FrameLowering.cpp400 MachineInstrBuilder MIB = in emitEpilogue() local
403 AddDefaultPred(MIB); in emitEpilogue()
404 MIB.copyImplicitOps(&*MBBI); in emitEpilogue()
424 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); in spillCalleeSavedRegisters() local
425 AddDefaultPred(MIB); in spillCalleeSavedRegisters()
443 MIB.addReg(Reg, getKillRegState(isKill)); in spillCalleeSavedRegisters()
445 MIB.setMIFlags(MachineInstr::FrameSetup); in spillCalleeSavedRegisters()
463 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); in restoreCalleeSavedRegisters() local
464 AddDefaultPred(MIB); in restoreCalleeSavedRegisters()
474 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); in restoreCalleeSavedRegisters()
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DThumb2InstrInfo.cpp157 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot() local
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
160 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO); in storeRegToStackSlot()
161 AddDefaultPred(MIB); in storeRegToStackSlot()
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); in loadRegFromStackSlot() local
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
202 AddDefaultPred(MIB); in loadRegFromStackSlot()
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DARMFastISel.cpp217 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
219 const MachineInstrBuilder &MIB,
265 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { in AddOptionalDefs() argument
266 MachineInstr *MI = &*MIB; in AddOptionalDefs()
272 AddDefaultPred(MIB); in AddOptionalDefs()
279 AddDefaultT1CC(MIB); in AddOptionalDefs()
281 AddDefaultCC(MIB); in AddOptionalDefs()
283 return MIB; in AddOptionalDefs()
631 MachineInstrBuilder MIB; in ARMMaterializeGV() local
634 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), in ARMMaterializeGV()
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DARMInstrInfo.cpp128 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL, in runOnMachineFunction() local
132 MIB.addImm(0); in runOnMachineFunction()
133 AddDefaultPred(MIB); in runOnMachineFunction()
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg) in runOnMachineFunction()
143 AddDefaultPred(MIB); in runOnMachineFunction()
DARMBaseInstrInfo.h136 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
327 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { in AddDefaultPred() argument
328 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); in AddDefaultPred()
332 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { in AddDefaultCC() argument
333 return MIB.addReg(0); in AddDefaultCC()
337 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
339 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
343 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { in AddNoT1CC() argument
344 return MIB.addReg(0); in AddNoT1CC()
DMLxExpansionPass.cpp293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction() local
297 MIB.addImm(LaneImm); in ExpandFPMLxInstruction()
298 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
300 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2) in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
310 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
DARMLoadStoreOptimizer.cpp515 MachineInstrBuilder MIB; in MergeOps() local
522 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)); in MergeOps()
525 MIB.addReg(Base, getDefRegState(true)) in MergeOps()
535 MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)); in MergeOps()
536 MIB.addReg(Base, getKillRegState(BaseKill)); in MergeOps()
539 MIB.addImm(Pred).addReg(PredReg); in MergeOps()
542 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) in MergeOps()
547 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); in MergeOps()
1053 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple() local
1060 MIB.addOperand(MI->getOperand(OpNum)); in MergeBaseUpdateLSMultiple()
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DARMFrameLowering.cpp674 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); in emitEpilogue() local
676 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), in emitEpilogue()
680 MIB.addExternalSymbol(JumpTarget.getSymbolName(), in emitEpilogue()
685 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); in emitEpilogue()
849 MachineInstrBuilder MIB = in emitPushInst() local
853 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
855 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), in emitPushInst() local
860 AddDefaultPred(MIB); in emitPushInst()
922 MachineInstrBuilder MIB = in emitPopInst() local
926 MIB.addReg(Regs[i], getDefRegState(true)); in emitPopInst()
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/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr() local
107 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
109 MIB.addImm(Cond[i].getImm()); in BuildCondBr()
113 MIB.addMBB(TBB); in BuildCondBr()
287 MachineInstrBuilder MIB; in genInstrWithNewOpc() local
288 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
291 MIB.addOperand(I->getOperand(J)); in genInstrWithNewOpc()
293 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end()); in genInstrWithNewOpc()
294 return MIB; in genInstrWithNewOpc()
DMips16InstrInfo.cpp87 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg() local
90 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
93 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
173 static void addSaveRestoreRegs(MachineInstrBuilder &MIB, in addSaveRestoreRegs() argument
186 MIB.addReg(Reg, Flags); in addSaveRestoreRegs()
205 MachineInstrBuilder MIB; in makeFrame() local
207 MIB = BuildMI(MBB, I, DL, get(Opc)); in makeFrame()
209 addSaveRestoreRegs(MIB, CSI); in makeFrame()
211 MIB.addReg(Mips::S2); in makeFrame()
213 MIB.addImm(FrameSize); in makeFrame()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrBuilder.h33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
/external/llvm/lib/Target/SystemZ/
DSystemZFrameLowering.cpp109 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, in addSavedGPR() argument
115 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive)); in addSavedGPR()
174 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG)); in spillCalleeSavedRegisters() local
177 addSavedGPR(MBB, MIB, LowGPR, false); in spillCalleeSavedRegisters()
178 addSavedGPR(MBB, MIB, HighGPR, false); in spillCalleeSavedRegisters()
181 MIB.addReg(SystemZ::R15D).addImm(StartOffset); in spillCalleeSavedRegisters()
188 addSavedGPR(MBB, MIB, Reg, true); in spillCalleeSavedRegisters()
194 addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true); in spillCalleeSavedRegisters()
244 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG)); in restoreCalleeSavedRegisters() local
247 MIB.addReg(LowGPR, RegState::Define); in restoreCalleeSavedRegisters()
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DSystemZInstrBuilder.h27 addFrameReference(const MachineInstrBuilder &MIB, int FI) { in addFrameReference() argument
28 MachineInstr *MI = MIB; in addFrameReference()
43 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO); in addFrameReference()
/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp97 MachineInstrBuilder MIB = in tryOrrMovk() local
114 transferImpOps(MI, MIB, MIB1); in tryOrrMovk()
164 MachineInstrBuilder MIB = in tryToreplicateChunks() local
195 transferImpOps(MI, MIB, MIB1); in tryToreplicateChunks()
216 transferImpOps(MI, MIB, MIB2); in tryToreplicateChunks()
347 MachineInstrBuilder MIB = in trySequenceOfOnes() local
369 transferImpOps(MI, MIB, MIB1); in trySequenceOfOnes()
383 transferImpOps(MI, MIB, MIB2); in trySequenceOfOnes()
402 MachineInstrBuilder MIB = in expandMOVImm() local
407 transferImpOps(MI, MIB, MIB); in expandMOVImm()
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DAArch64LoadStoreOptimizer.cpp311 MachineInstrBuilder MIB = BuildMI(*I->getParent(), InsertionPoint, in mergePairedInsns() local
317 (void)MIB; in mergePairedInsns()
327 DEBUG(((MachineInstr *)MIB)->print(dbgs())); in mergePairedInsns()
539 MachineInstrBuilder MIB = in mergePreIdxUpdateInsn() local
545 (void)MIB; in mergePreIdxUpdateInsn()
553 DEBUG(((MachineInstr *)MIB)->print(dbgs())); in mergePreIdxUpdateInsn()
582 MachineInstrBuilder MIB = in mergePostIdxUpdateInsn() local
588 (void)MIB; in mergePostIdxUpdateInsn()
596 DEBUG(((MachineInstr *)MIB)->print(dbgs())); in mergePostIdxUpdateInsn()
/external/llvm/lib/CodeGen/
DMachineInstrBundle.cpp110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(), in finalizeBundle() local
112 Bundle.prepend(MIB); in finalizeBundle()
191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
/external/llvm/lib/Target/R600/
DR600InstrInfo.cpp1032 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); in PredicateInstruction() local
1033 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1040 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); in PredicateInstruction() local
1041 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1192 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode), in buildDefaultInstruction() local
1196 MIB.addImm(0) // $update_exec_mask in buildDefaultInstruction()
1199 MIB.addImm(1) // $write in buildDefaultInstruction()
1210 MIB.addReg(Src1Reg) // $src1 in buildDefaultInstruction()
1219 MIB.addImm(1) // $last in buildDefaultInstruction()
1224 return MIB; in buildDefaultInstruction()
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