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Searched refs:MRM6r (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h297 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
683 case X86II::MRM6r: case X86II::MRM7r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp923 case X86II::MRM6r: case X86II::MRM7r: in EmitVEXOpcodePrefix()
1428 case X86II::MRM6r: case X86II::MRM7r: { in EncodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp96 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
686 case X86Local::MRM6r: in emitInstructionSpecifier()
826 case X86Local::MRM6r: case X86Local::MRM7r: in emitDecodePath()
/external/llvm/lib/Target/X86/
DX86InstrMMX.td449 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
452 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
455 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
DX86InstrFPStack.td260 def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">;
261 def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;
262 def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">;
578 def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg),
580 def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg),
DX86InstrInfo.td967 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
971 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1009 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1552 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1555 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1558 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1929 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1932 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1935 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2290 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
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DX86CodeEmitter.cpp960 case X86II::MRM6r: case X86II::MRM7r: in emitVEXOpcodePrefix()
1306 case X86II::MRM6r: case X86II::MRM7r: { in emitInstruction()
DX86InstrArithmetic.td298 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
301 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
304 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
308 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
1228 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
DX86InstrSystem.td459 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
DX86InstrSSE.td4148 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4151 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4154 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4194 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4197 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4200 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4240 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4243 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4246 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
DX86InstrFormats.td32 def MRM6r : Format<22>; def MRM7r : Format<23>;
DX86InstrAVX512.td2571 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2578 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
/external/llvm/test/TableGen/
DTargetInstrInfo.td54 def MRM6r : Format<22>; def MRM7r : Format<23>;
/external/llvm/docs/
DWritingAnLLVMBackend.rst1823 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data