| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 297 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
683 case X86II::MRM6r: case X86II::MRM7r: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 923 case X86II::MRM6r: case X86II::MRM7r: in EmitVEXOpcodePrefix()
1428 case X86II::MRM6r: case X86II::MRM7r: { in EncodeInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 226 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
230 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
234 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
238 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
244 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
248 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
252 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
256 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
263 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
267 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
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| D | X86CodeEmitter.cpp | 960 case X86II::MRM6r: case X86II::MRM7r: in emitVEXOpcodePrefix()
1306 case X86II::MRM6r: case X86II::MRM7r: { in emitInstruction()
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| D | X86InstrFPStack.td | 257 def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">;
258 def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">;
259 def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">;
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| D | X86InstrArithmetic.td | 335 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
338 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
341 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
345 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
1244 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
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| D | X86InstrInfo.td | 1508 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1511 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1514 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1944 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1947 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1950 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2296 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
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| D | X86InstrFormats.td | 32 def MRM6r : Format<22>; def MRM7r : Format<23>;
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| D | X86InstrSSE.td | 4177 def VPSLLDQri : PDIi8<0x73, MRM7r,
4223 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4269 def PSLLDQri : PDIi8<0x73, MRM7r,
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 96 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
134 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)); in isRegFormat()
687 case X86Local::MRM7r: in emitInstructionSpecifier()
826 case X86Local::MRM6r: case X86Local::MRM7r: in emitDecodePath()
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 54 def MRM6r : Format<22>; def MRM7r : Format<23>;
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1823 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
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