| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
88 "mov $dst, $src", 0x88, MRMDestReg,
102 "and $dst, $src2", 0x20, MRMDestReg,
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrVMX.td | 48 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
52 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
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| D | X86InstrSystem.td | 125 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
128 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
144 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
147 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
175 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
177 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
179 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
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| D | X86InstrShiftRotate.td | 691 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
697 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
703 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
708 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
713 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
719 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
728 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
735 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
742 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
749 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
[all …]
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| D | X86InstrInfo.td | 1174 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1176 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1178 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1180 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1379 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1412 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1416 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1420 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1486 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1489 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
[all …]
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| D | X86InstrMMX.td | 233 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
248 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
258 def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
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| D | X86InstrAVX512.td | 226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
537 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
1379 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1383 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1388 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1541 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
[all …]
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| D | X86InstrSSE.td | 550 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
933 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
937 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
941 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
945 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
949 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
953 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
957 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
961 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
1010 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
[all …]
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| D | X86CodeEmitter.cpp | 942 case X86II::MRMDestReg: in emitVEXOpcodePrefix()
1238 case X86II::MRMDestReg: { in emitInstruction()
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| D | X86InstrArithmetic.td | 707 Format f = MRMDestReg>
725 SDPatternOperator opnode, Format f = MRMDestReg>
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| D | X86InstrFormats.td | 22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 241 MRMDestReg = 3, enumerator
655 case X86II::MRMDestReg: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 892 case X86II::MRMDestReg: in EmitVEXOpcodePrefix()
1342 case X86II::MRMDestReg: in EncodeInstruction()
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 84 MRMDestReg = 3, enumerator
131 return (form == X86Local::MRMDestReg || in isRegFormat()
561 case X86Local::MRMDestReg: in emitInstructionSpecifier()
818 case X86Local::MRMDestReg: case X86Local::MRMDestMem: in emitDecodePath()
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| /external/llvm/docs/TableGen/ |
| D | index.rst | 131 Format Form = MRMDestReg;
164 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1808 case X86II::MRMDestReg:// for instructions that use the Mod/RM byte
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