Searched refs:OpReg (Results 1 – 6 of 6) sorted by relevance
1438 unsigned OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local1439 if (OpReg == 0) return false; in X86SelectBranch()1441 .addReg(OpReg).addImm(1); in X86SelectBranch()1483 unsigned OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local1484 if (OpReg == 0) return false; in X86SelectBranch()1487 .addReg(OpReg).addImm(1); in X86SelectBranch()1500 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local1506 case Instruction::LShr: OpReg = X86::SHR8rCL; break; in X86SelectShift()1507 case Instruction::AShr: OpReg = X86::SAR8rCL; break; in X86SelectShift()1508 case Instruction::Shl: OpReg = X86::SHL8rCL; break; in X86SelectShift()[all …]
304 unsigned OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local306 if (!TRI->isVirtualRegister(OpReg)) in optimizeSDPattern()309 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
1288 unsigned OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local1289 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()1292 .addReg(OpReg).addImm(1)); in SelectBranch()
1009 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); in SelectFNeg() local1010 if (OpReg == 0) return false; in SelectFNeg()1017 ISD::FNEG, OpReg, OpRegIsKill); in SelectFNeg()1031 ISD::BITCAST, OpReg, OpRegIsKill); in SelectFNeg()
1751 unsigned OpReg = MO.getReg(); in clearRegisterKills() local1752 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg))) in clearRegisterKills()
5595 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local5596 if (OpReg == Reg) in checkLowRegisterList()5599 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()5609 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local5610 if (OpReg == Reg) in listContainsReg()