Home
last modified time | relevance | path

Searched refs:R6 (Results 1 – 25 of 71) sorted by relevance

123

/external/llvm/test/CodeGen/Mips/
Dselect.ll3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6
21 ; 32R6-DAG: seleqz $[[T0:[0-9]+]], $5, $4
22 ; 32R6-DAG: selnez $[[T1:[0-9]+]], $6, $4
23 ; 32R6: or $2, $[[T1]], $[[T0]]
31 ; 64R6-DAG: seleqz $[[T0:[0-9]+]], $5, $4
32 ; 64R6-DAG: selnez $[[T1:[0-9]+]], $6, $4
33 ; 64R6: or $2, $[[T1]], $[[T0]]
58 ; 32R6-DAG: lw $[[F1:[0-9]+]], 16($sp)
59 ; 32R6-DAG: seleqz $[[T0:[0-9]+]], $6, $4
[all …]
Dmadd-msub.ll3 ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R6
7 ; RUN: llc -march=mips -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64R6
26 ; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
27 ; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6
28 ; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
29 ; 32R6-DAG: sra $[[T3:[0-9]+]], $6, 31
30 ; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
31 ; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
32 ; 32R6-DAG: addu $2, $[[T5]], $[[T4]]
41 ; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
[all …]
Dzeroreg.ll3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6
7 ; RUN: llc < %s -march=mipsel -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6
18 ; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
19 ; 32R6: seleqz $2, $[[R0]], $4
24 ; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
25 ; 64R6: seleqz $2, $[[R0]], $4
40 ; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
41 ; 32R6: selnez $2, $[[R0]], $4
46 ; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
47 ; 64R6: selnez $2, $[[R0]], $4
[all …]
Dmno-ldc1-sdc1.ll7 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6-LDC1
20 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \
21 ; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-PIC
34 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \
35 ; RUN: -check-prefix=32R6-BE -check-prefix=32R6-BE-PIC
48 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \
49 ; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-STATIC
65 ; 32R6-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
66 ; 32R6-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
67 ; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0
[all …]
Dfmadd1.ll10 …enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NONAN
13 …enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NONAN
16 …mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NAN
19 …mcpu=mips64r6 -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NAN
36 ; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
37 ; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
38 ; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
39 ; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
40 ; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
51 ; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
[all …]
Dcountleading.ll3 ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6 …
55 ; MIPS32-R6-DAG: seleqz $[[R5:[0-9]+]], $[[R2]], $5
56 ; MIPS32-R6-DAG: selnez $[[R6:[0-9]+]], $[[R1]], $5
57 ; MIPS32-R6-DAG: or $2, $[[R6]], $[[R5]]
80 ; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]]
81 ; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]]
82 ; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]]
Deh-return64.ll1 …mips64el -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
2 …mips64el -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
3 …mips64el -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
4 …rch=mips64el -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6
47 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
48 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
89 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
90 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
Deh-return32.ll1 …h=mipsel -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
2 …h=mipsel -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
3 …march=mipsel -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6
46 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
47 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
86 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
87 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
Dcttz-v.ll15 ; MIPS32-DAG: not $[[R6:[0-9]+]], $5
16 ; MIPS32-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]]
28 ; MIPS64-DAG: not $[[R6:[0-9]+]], $5
29 ; MIPS64-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]]
Datomic.ll111 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
112 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
150 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
151 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
189 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
190 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
229 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
230 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
268 ; ALL: ori $[[R6:[0-9]+]], $zero, 255
269 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll10 …%s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
11 … < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
12 …inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
13 … < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
14 … < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
15 … < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
16 …inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
21 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
22 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
31 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
[all …]
Dindirectbr.ll3 …rch=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
4 …rch=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
5 … -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
6 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
7 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
8 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
9 … -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
13 ; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR
14 ; R6: jr $4 # <MCInst #{{[0-9]+}} JALR
17 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
[all …]
Dcall.ll69 ; NOT-R6: jr $[[TGT]]
70 ; R6: r6.jr $[[TGT]]
83 ; NOT-R6: jr $[[TGT]]
84 ; R6: r6.jr $[[TGT]]
97 ; NOT-R6: jr $[[TGT]]
98 ; R6: r6.jr $[[TGT]]
/external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/lc3b/tests/
Dlc3b-mp22NC.asm9 LD R6, R2, CDATA3F-CC
17 RSHFL R6, R7, 8
20 STB R6, R3, 0
30 STB R6, R3, 0
35 LD R6, R1, BDATA35-BB
36 ST R6, R2, CDATA37-CC
41 LD R6, R2, CDATA35-CC
56 LD R6, R1, BDATA0-BB
57 LD R6, R1, BDATA4-BB
58 LD R6, R1, BDATA10-BB
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s136 LDR R6,[sp,#44]
142 SUB R10,R6,R3 @// luma offset
152 ADD R7,R0,R6 @// luma_next_row = luma + luma_stride
162 MOV R6,R3, LSR #4 @// width_cnt = width / 16
171 SUBS R6,R6,#1
308 SUBS R6,R6,#1 @// width_cnt -= 1
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td32 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
/external/llvm/test/CodeGen/Mips/msa/
D3r-b.ll118 ; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])
119 ; CHECK-DAG: binsl.b [[R4]], [[R5]], [[R6]]
146 ; CHECK-DAG: ld.h [[R6:\$w[0-9]+]], 0([[R3]])
147 ; CHECK-DAG: binsl.h [[R4]], [[R5]], [[R6]]
174 ; CHECK-DAG: ld.w [[R6:\$w[0-9]+]], 0([[R3]])
175 ; CHECK-DAG: binsl.w [[R4]], [[R5]], [[R6]]
202 ; CHECK-DAG: ld.d [[R6:\$w[0-9]+]], 0([[R3]])
203 ; CHECK-DAG: binsl.d [[R4]], [[R5]], [[R6]]
230 ; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])
231 ; CHECK-DAG: binsr.b [[R4]], [[R5]], [[R6]]
[all …]
Dvec.ll189 ; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])
190 ; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]
219 ; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])
220 ; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]
249 ; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])
250 ; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]
279 ; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])
280 ; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]
309 ; ANYENDIAN-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])
311 ; ANYENDIAN-DAG: bmnz.v [[R5]], [[R4]], [[R6]]
[all …]
/external/llvm/include/llvm/Support/
DMathExtras.h231 #define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4) macro
232 R6(0), R6(2), R6(1), R6(3)
235 #undef R6
/external/llvm/lib/Target/SystemZ/
DSystemZCallingConv.td24 // care about the ABI. (R6 is an argument register too, but is
54 // The first 5 integer arguments are passed in R2-R6. Note that R6
/external/llvm/test/TableGen/
DForeachList.td70 // CHECK: def R6
71 // CHECK: string Name = "R6";
DForeachLoop.td46 // CHECK: def R6
47 // CHECK: string Name = "R6";
/external/bison/tests/
Doutput.at350 11 -> "11R6" [style=solid]
351 "11R6" [label="R6", fillcolor=3, shape=diamond, style=filled]
409 10 -> "10R6" [style=solid]
410 "10R6" [label="R6", fillcolor=3, shape=diamond, style=filled]
500 11 -> "11R6" [style=solid]
501 "11R6" [label="R6", fillcolor=3, shape=diamond, style=filled]
577 "12R6d" [label="R6", fillcolor=5, shape=diamond, style=filled]
578 12 -> "12R6" [style=solid]
579 "12R6" [label="R6", fillcolor=3, shape=diamond, style=filled]
/external/llvm/lib/Target/ARM/
DARMCallingConv.td106 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
205 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
212 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
218 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
220 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
/external/llvm/test/CodeGen/ARM/
Dlsr-code-insertion.ll10 ; CHECK: ldr [[R6:r[0-9*]+]], LCP
11 ; CHECK: cmp {{.*}}, [[R6]]

123