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Searched refs:RAX (Results 1 – 25 of 50) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dabi-isel.ll56 ; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r..]]
57 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
85 ; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
86 ; DARWIN-64-STATIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
92 ; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
93 ; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
99 ; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
100 ; DARWIN-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
128 ; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
129 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
[all …]
Dobject-size.ll15 ; X64: movabsq $-1, [[RAX:%r..]]
16 ; X64: cmpq $-1, [[RAX]]
D2009-09-19-earlyclobber.ll4 ; Registers other than RAX, RCX are OK, but they must be different.
D2010-02-12-CoalescerBug-Impdef.ll5 ; After coalescing %RAX with a virtual register, this instruction was rematted:
9 ; This instruction silently defined %RAX, and when rematting removed the
10 ; instruction, the live interval for %RAX was not properly updated. The valno
13 ; The fix is to implicitly define %RAX when coalescing:
15 ; %EAX<def> = MOV32rr %reg1070<kill>, %RAX<imp-def>
D2010-04-08-CoalescerBug.ll5 ; %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>
Dcritical-anti-dep-breaker.ll6 ; There is an anti-dependency (WAR) hazard using RAX using default reg allocation and scheduling.
Dtailcall-64.ll184 ; CHECK: leaq (%rsi,%rsi,4), %[[RAX:r..]]
185 ; CHECK: jmpq *16(%{{r..}},%[[RAX]],8) # TAILCALL
Dmisched-new.ll17 ; After coalescing, we have a dead superreg (RAX) definition.
/external/llvm/test/MC/X86/
Dintel-syntax.s19 mov RAX, QWORD PTR [RSP]
25 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
65 mov RAX, QWORD PTR FS:[320]
67 mov RAX, QWORD PTR FS:320
69 mov QWORD PTR FS:320, RAX
71 mov QWORD PTR FS:20[rbx], RAX
380 shld [RAX], BX
381 shld [RAX], BX, CL
385 shrd [RAX], BX
386 shrd [RAX], BX, CL
[all …]
Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
/external/llvm/lib/Target/X86/
DX86InstrSVM.td35 let Uses = [RAX] in
43 let Uses = [RAX] in
51 let Uses = [RAX] in
59 let Uses = [RAX, ECX] in
DX86InstrArithmetic.td78 // RAX,RDX = RAX*GR64
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
104 // RAX,RDX = RAX*[mem64]
105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
123 // RAX,RDX = RAX*GR64
124 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
143 // RAX,RDX = RAX*[mem64]
144 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
306 // RDX:RAX/r64 = RAX,RDX
[all …]
DX86InstrExtension.td30 let Defs = [RAX], Uses = [EAX] in
32 "{cltq|cdqe}", [], IIC_CBW>; // RAX = signext(EAX)
34 let Defs = [RAX,RDX], Uses = [RAX] in
36 "{cqto|cqo}", [], IIC_CBW>; // RDX:RAX = signext(RAX)
DX86MCInstLower.cpp250 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
277 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
311 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortMoveForm()
693 BaseReg = X86::RAX; ScaleVal = 1; in EmitNops()
701 IndexReg = X86::RAX; break; in EmitNops()
703 IndexReg = X86::RAX; break; in EmitNops()
706 IndexReg = X86::RAX; break; in EmitNops()
708 IndexReg = X86::RAX; break; in EmitNops()
710 IndexReg = X86::RAX; SegmentReg = X86::CS; break; in EmitNops()
888 .addReg(X86::RAX)); in EmitInstruction()
DX86InstrSystem.td17 let Defs = [RAX, RDX] in
21 let Defs = [RAX, RCX, RDX] in
443 let Defs = [RAX, RDX], Uses = [ECX] in
467 let Defs = [RAX, RBX, RCX, RDX], Uses = [RAX, RCX] in
482 let Defs = [RDX, RAX], Uses = [RCX] in
485 let Uses = [RDX, RAX, RCX] in
488 let Uses = [RDX, RAX] in {
506 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
519 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
523 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
DX86RegisterInfo.cpp550 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
562 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
599 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
635 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
671 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
672 return X86::RAX; in getX86SubSuperRegister()
DX86CallingConv.td38 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
138 // The X86-Win64 calling convention always returns __m64 values in RAX.
151 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
159 // Return: RAX
160 CCIfType<[i64], CCAssignToReg<[RAX]>>
362 CCIfType<[i64], CCAssignToReg<[RAX]>>,
618 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
624 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
637 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,
639 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,
DX86RegisterInfo.td129 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
339 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
363 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
365 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
367 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
386 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
390 // to clear upper 32-bits of RAX so is not a NOP.
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmInstrumentation.cpp357 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX)); in InstrumentMemOperandSmallImpl()
369 Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI)); in InstrumentMemOperandSmallImpl()
370 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX) in InstrumentMemOperandSmallImpl()
371 .addReg(X86::RAX).addImm(3)); in InstrumentMemOperandSmallImpl()
378 X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc())); in InstrumentMemOperandSmallImpl()
430 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX)); in InstrumentMemOperandSmallImpl()
438 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX)); in InstrumentMemOperandLargeImpl()
444 Inst.addOperand(MCOperand::CreateReg(X86::RAX)); in InstrumentMemOperandLargeImpl()
448 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX) in InstrumentMemOperandLargeImpl()
449 .addReg(X86::RAX).addImm(3)); in InstrumentMemOperandLargeImpl()
[all …]
/external/libunwind/src/x86_64/
Dinit.h49 c->dwarf.loc[RAX] = REG_INIT_LOC(c, rax, RAX); in common_init()
Dunwind_i.h39 #define RAX 0 macro
DGregs.c104 loc = c->dwarf.loc[(reg == UNW_X86_64_RAX) ? RAX : RDX]; in tdep_access_reg()
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h39 #define RAX 80 macro
/external/lzma/Asm/x86/
D7zAsm.asm62 r0 equ RAX
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h171 ENTRY(RAX) \
189 ENTRY(RAX) \

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