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Searched refs:Rm (Results 1 – 25 of 47) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMInstrThumb.td344 let Inst{6-3} = 0b1111; // Rm = pc
395 // ADD <Rm>, sp
407 // ADD sp, <Rm>
408 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
409 "add", "\t$Rdn, $Rm", []>,
412 bits<4> Rm;
414 let Inst{6-3} = Rm;
425 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
428 bits<4> Rm;
429 let Inst{6-3} = Rm;
[all …]
DARMInstrThumb2.td279 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
285 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
375 bits<4> Rm;
378 let Inst{3-0} = Rm;
385 bits<4> Rm;
388 let Inst{3-0} = Rm;
395 bits<4> Rm;
398 let Inst{3-0} = Rm;
434 bits<4> Rm;
438 let Inst{3-0} = Rm;
[all …]
DARMInstrInfo.td1224 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1225 iir, opc, "\t$Rd, $Rn, $Rm",
1226 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1230 bits<4> Rm;
1236 let Inst{3-0} = Rm;
1297 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1298 iir, opc, "\t$Rd, $Rn, $Rm",
1303 bits<4> Rm;
1306 let Inst{3-0} = Rm;
1359 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
[all …]
DARMInstrNEON.td667 let Rm = 0b1111;
675 let Rm = 0b1111;
696 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
701 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
702 "vld1", Dt, "$Vd, $Rn, $Rm",
713 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
718 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
719 "vld1", Dt, "$Vd, $Rn, $Rm",
740 let Rm = 0b1111;
749 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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DARMSchedule.td18 // Rd <- ADD Rn, Rm, <shift> Rs
20 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
23 // Rd after a minimum of three cycles after the result in Rm and Rs is available
28 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
DARMInstrFormats.td654 // {11-0} imm12/Rm
672 // {11-0} imm12/Rm
691 // {13} 1 == Rm, 0 == imm12
693 // {11-0} imm12/Rm
711 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
718 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
743 // {13} 1 == imm8, 0 == Rm
747 // {3-0} imm3_0/Rm
769 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
776 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
[all …]
DARMBaseInstrInfo.cpp2654 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2655 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
2661 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2662 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
2691 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2692 if (!Rm) in getNumMicroOpsSwiftLdSt()
2694 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
2704 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2705 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
2723 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
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/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td46 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
48 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
49 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
51 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
61 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
63 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
64 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
66 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
76 def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
78 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
[all …]
DAArch64InstrFormats.td1204 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1205 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1210 bits<5> Rm;
1213 let Inst{20-16} = Rm;
1222 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1227 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1258 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1259 asm, "\t$Rd, $Rn, $Rm", "",
1260 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1263 bits<5> Rm;
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DAArch64InstrInfo.td532 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
533 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
534 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
535 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
536 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
537 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
538 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
539 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
616 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
617 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
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/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1138 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegImmOperand() local
1143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegImmOperand()
1175 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegRegOperand() local
1180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegRegOperand()
1475 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode2IdxInstruction() local
1537 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1579 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegMemOperand() local
1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegMemOperand()
1624 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode3Instruction() local
1657 if (type && Rm == 15) in DecodeAddrMode3Instruction()
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/external/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp739 uint32_t Rm; // the source register in EmulateMOVRdRm() local
745 Rm = Bits32(opcode, 6, 3); in EmulateMOVRdRm()
752 Rm = Bits32(opcode, 5, 3); in EmulateMOVRdRm()
759 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
762 if (setflags && (BadReg(Rd) || BadReg(Rm))) in EmulateMOVRdRm()
765 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13))) in EmulateMOVRdRm()
770 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
780 uint32_t result = ReadCoreReg(Rm, &success); in EmulateMOVRdRm()
788 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg); in EmulateMOVRdRm()
1124 uint32_t Rm; // the source register in EmulateMVNReg() local
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/external/vixl/src/a64/
Dsimulator-a64.cc622 reg(reg_size, instr->Rm()), in VisitAddSubShifted()
638 reg(reg_size, instr->Rm()), in VisitAddSubExtended()
647 int64_t op2 = reg(reg_size, instr->Rm()); in VisitAddSubWithCarry()
668 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, in VisitLogicalShifted()
712 ConditionalCompareHelper(instr, reg(reg_size, instr->Rm())); in VisitConditionalCompareRegister()
767 int64_t offset = ExtendValue(kXRegSize, xreg(instr->Rm()), ext, in VisitLoadStoreRegisterOffset()
1062 new_val = xreg(instr->Rm()); in VisitConditionalSelect()
1151 int32_t rm = wreg(instr->Rm()); in VisitDataProcessing2Source()
1164 int64_t rm = xreg(instr->Rm()); in VisitDataProcessing2Source()
1177 uint32_t rm = static_cast<uint32_t>(wreg(instr->Rm())); in VisitDataProcessing2Source()
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Dassembler-a64.cc705 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
714 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
723 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
732 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
777 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.size()) | Rn(rn) | Rd(rd)); in extr()
852 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd)); in ConditionalSelect()
877 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd)); in DataProcessing3Source()
967 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd)); in sdiv()
983 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd)); in udiv()
1391 Emit(FPType(fn) | FCMP | Rm(fm) | Rn(fn)); in fcmp()
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Ddisasm-a64.h78 return (instr->Rm() == kZeroRegCode); in RmIsZROrSP()
Ddisasm-a64.cc379 bool rn_is_rm = (instr->Rn() == instr->Rm()); in VisitConditionalSelect()
515 if (instr->Rn() == instr->Rm()) { in VisitExtract()
1313 case 'm': reg_num = instr->Rm(); break; in SubstituteRegisterField()
1652 unsigned rm = instr->Rm(); in SubstituteLSRegOffsetField()
/external/chromium_org/v8/src/arm/
Ddisasm-arm.cc91 void FormatNeonMemory(int Rn, int align, int Rm);
416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { in FormatNeonMemory() argument
423 if (Rm == 15) { in FormatNeonMemory()
425 } else if (Rm == 13) { in FormatNeonMemory()
429 "], r%d", Rm); in FormatNeonMemory()
1574 int Rm = instr->VmValue(); in DecodeSpecialCondition() local
1579 FormatNeonMemory(Rn, align, Rm); in DecodeSpecialCondition()
1587 int Rm = instr->VmValue(); in DecodeSpecialCondition() local
1592 FormatNeonMemory(Rn, align, Rm); in DecodeSpecialCondition()
/external/chromium_org/v8/src/arm64/
Dsimulator-arm64.cc864 T op2 = reg<T>(instr->Rm()); in AddSubWithCarry()
943 T op2 = reg<T>(instr->Rm()); in Extract()
1298 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1301 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1321 int64_t op2 = ExtendValue(xreg(instr->Rm()), ext, left_shift); in VisitAddSubExtended()
1324 int32_t op2 = ExtendValue(wreg(instr->Rm()), ext, left_shift); in VisitAddSubExtended()
1344 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1348 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1394 ConditionalCompareHelper(instr, xreg(instr->Rm())); in VisitConditionalCompareRegister()
1396 ConditionalCompareHelper(instr, wreg(instr->Rm())); in VisitConditionalCompareRegister()
[all …]
Dassembler-arm64.cc1017 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1026 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1035 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1044 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1095 Emit(SF(rd) | EXTR | N | Rm(rm) | in extr()
1171 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd)); in ConditionalSelect()
1196 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd)); in DataProcessing3Source()
1298 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd)); in sdiv()
1307 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd)); in udiv()
1721 Emit(FPType(fn) | FCMP | Rm(fm) | Rn(fn)); in fcmp()
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Ddisasm-arm64.h59 return (instr->Rm() == kZeroRegCode); in RmIsZROrSP()
/external/llvm/test/MC/Disassembler/AArch64/
Da64-ignored-fields.txt4 # The "Rm" bits are ignored, but the canonical representation has them filled
/external/chromium_org/tools/telemetry/
Dcloud_storage148 class Rm(command_line.Command): class
197 commands = (Ls, Mv, Rm, Upload)
/external/qemu/distrib/sdl-1.2.15/src/video/
DSDL_pixels.c143 int Rm=0,Gm=0,Bm=0; in SDL_AllocFormat() local
152 Rm|=1<<i; in SDL_AllocFormat()
155 fprintf(stderr,"Rw=%d Rm=0x%02X\n",Rw,Rm); in SDL_AllocFormat()
189 r=(r<<format->Rloss)|((r*Rm)>>Rw); in SDL_AllocFormat()
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp762 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeThreeAddrSRegInstruction() local
790 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
811 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1307 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeAddSubERegInstruction() local
1321 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1327 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1333 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1339 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1345 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1351 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
/external/llvm/docs/TableGen/
Dindex.rst241 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
244 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
248 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
252 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,

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