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Searched refs:SCVTF (Results 1 – 7 of 7) sorted by relevance

/external/vixl/src/a64/
Dconstants-a64.h1067 SCVTF = FPIntegerConvertFixed | 0x00020000, enumerator
1068 SCVTF_sw = SCVTF,
1069 SCVTF_sx = SCVTF | SixtyFourBits,
1070 SCVTF_dw = SCVTF | FP64,
1071 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
Dassembler-a64.cc1490 Emit(SF(rn) | FPType(fd) | SCVTF | Rn(rn) | Rd(fd)); in scvtf()
/external/chromium_org/v8/src/arm64/
Dconstants-arm64.h1183 SCVTF = FPIntegerConvertFixed | 0x00020000, enumerator
1184 SCVTF_sw = SCVTF,
1185 SCVTF_sx = SCVTF | SixtyFourBits,
1186 SCVTF_dw = SCVTF | FP64,
1187 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
Dassembler-arm64.cc1820 Emit(SF(rn) | FPType(fd) | SCVTF | Rn(rn) | Rd(fd)); in scvtf()
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-basic-a64-undefined.txt26 # SCVTF on fixed point W-registers is undefined if scale<5> == 0.
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2219 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2563 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2990 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
4197 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4271 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4442 // SCVTF GPR -> FPR is 9 cycles.
4443 // SCVTF FPR -> FPR is 4 cyclces.
4445 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4496 // SCVTF on floating point registers (both source and destination
DAArch64SchedCyclone.td572 // SCVTF,UCVTF V,V