| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 190 SDIVREM, UDIVREM, enumerator
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 866 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults() local
868 Results.push_back(SDIVREM); in ReplaceNodeResults()
875 SDValue SDIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults() local
877 Results.push_back(SDIVREM.getValue(1)); in ReplaceNodeResults()
880 case ISD::SDIVREM: { in ReplaceNodeResults()
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| D | AMDGPUISelLowering.cpp | 251 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
310 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
537 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 145 setOperationAction(ISD::SDIVREM, VT, Expand); in InitAMDILLowering()
167 setOperationAction(ISD::SDIVREM, VT, Expand); in InitAMDILLowering()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 145 setOperationAction(ISD::SDIVREM, VT, Expand); in InitAMDILLowering()
167 setOperationAction(ISD::SDIVREM, VT, Expand); in InitAMDILLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 172 case ISD::SDIVREM: return "sdivrem"; in getOperationName()
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| D | LegalizeDAG.cpp | 2196 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in useDivRem()
2224 bool isSigned = Opcode == ISD::SDIVREM; in ExpandDivRemLibCall()
3611 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3642 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3676 case ISD::SDIVREM: in ExpandNode()
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| D | DAGCombiner.cpp | 1215 case ISD::SDIVREM: return visitSDIVREM(N); in visit()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 134 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
136 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
211 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
366 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
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| D | MipsISelLowering.cpp | 386 setTargetDAGCombine(ISD::SDIVREM); in MipsTargetLowering()
437 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : in performDivRemCombine()
745 case ISD::SDIVREM: in PerformDAGCombine()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 155 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
161 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1324 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in HexagonTargetLowering()
1327 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2389 case ISD::SDIVREM: in Select()
2394 bool isSigned = Opcode == ISD::SDIVREM; in Select()
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| D | X86ISelLowering.cpp | 844 setOperationAction(ISD::SDIVREM, VT, Expand); in resetOperationActions()
1553 setOperationAction(ISD::SDIVREM, MVT::i128, Custom); in resetOperationActions()
15112 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break; in LowerWin64_i128OP()
16299 case ISD::SDIVREM: in ReplaceNodeResults()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 154 setOperationAction(ISD::SDIVREM, VT, Custom); in SystemZTargetLowering()
2433 case ISD::SDIVREM: in LowerOperation()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1406 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1413 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 328 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 683 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in ARMTargetLowering()
686 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in ARMTargetLowering()
6255 case ISD::SDIVREM: in LowerOperation()
10554 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
10556 bool isSigned = (Opcode == ISD::SDIVREM); in LowerDivRem()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in PPCTargetLowering()
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in PPCTargetLowering()
459 setOperationAction(ISD::SDIVREM, VT, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 249 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
250 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
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