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Searched refs:SDValue (Results 1 – 25 of 113) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h86 SmallDenseMap<SDValue, SDValue, 8> PromotedIntegers;
90 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedIntegers;
94 SmallDenseMap<SDValue, SDValue, 8> SoftenedFloats;
98 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedFloats;
102 SmallDenseMap<SDValue, SDValue, 8> ScalarizedVectors;
106 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> SplitVectors;
110 SmallDenseMap<SDValue, SDValue, 8> WidenedVectors;
114 SmallDenseMap<SDValue, SDValue, 8> ReplacedValues;
138 ReplacedValues[SDValue(Old, i)] = SDValue(New, i); in NoteDeletion()
145 void AnalyzeNewValue(SDValue &Val);
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/external/llvm/include/llvm/Target/
DTargetSelectionDAGInfo.h56 virtual SDValue
58 SDValue Chain, in EmitTargetCodeForMemcpy()
59 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy()
60 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemcpy()
64 return SDValue(); in EmitTargetCodeForMemcpy()
73 virtual SDValue
75 SDValue Chain, in EmitTargetCodeForMemmove()
76 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove()
77 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
80 return SDValue(); in EmitTargetCodeForMemmove()
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/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h33 unsigned getMSACtrlReg(const SDValue RegIdx) const;
40 SDNode *selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
43 bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
44 bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
47 bool selectAddrRegImm(SDValue Addr, SDValue &Base,
48 SDValue &Offset) const override;
50 bool selectAddrRegReg(SDValue Addr, SDValue &Base,
51 SDValue &Offset) const override;
53 bool selectAddrDefault(SDValue Addr, SDValue &Base,
54 SDValue &Offset) const override;
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DMipsISelDAGToDAG.h57 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
58 SDValue &Offset) const;
62 virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
63 SDValue &Offset) const;
66 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
67 SDValue &Offset) const;
70 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
71 SDValue &Offset) const;
73 virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
74 SDValue &Offset) const;
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DMipsISelDAGToDAG.cpp68 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, in selectAddrRegImm()
69 SDValue &Offset) const { in selectAddrRegImm()
74 bool MipsDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base, in selectAddrRegReg()
75 SDValue &Offset) const { in selectAddrRegReg()
80 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, in selectAddrDefault()
81 SDValue &Offset) const { in selectAddrDefault()
86 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, in selectIntAddr()
87 SDValue &Offset) const { in selectIntAddr()
92 bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, in selectIntAddrMM()
93 SDValue &Offset) const { in selectIntAddrMM()
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DMipsISelLowering.h229 SmallVectorImpl<SDValue> &Results,
233 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
238 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
248 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
261 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
268 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG, in getAddrLocal()
272 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
274 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, in getAddrLocal()
278 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
288 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG, in getAddrGlobal()
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/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h179 SDValue Root;
323 const SDValue &getRoot() const { return Root; }
327 SDValue getEntryNode() const {
328 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
333 const SDValue &setRoot(SDValue N) {
399 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false,
401 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false,
403 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false,
405 SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false);
406 SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque = false) {
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.h100 bool isZExtFree(SDValue Val, EVT VT2) const override;
107 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
112 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
130 SDValue LowerCCCArguments(SDValue Chain,
135 SmallVectorImpl<SDValue> &InVals) const;
136 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
140 const SmallVectorImpl<SDValue> &OutVals,
143 SmallVectorImpl<SDValue> &InVals) const;
144 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
145 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
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/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h339 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
361 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
362 SDValue &Offset,
369 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
376 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
381 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
388 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
393 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
396 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
400 void computeKnownBitsForTargetNode(const SDValue Op,
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/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.h32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
34 SDValue Chain,
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
46 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
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DR600ISelLowering.h29 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
30 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
32 SmallVectorImpl<SDValue> &Results,
34 SDValue LowerFormalArguments(
35 SDValue Chain,
40 SmallVectorImpl<SDValue> &InVals) const override;
48 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
53 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const;
54 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
56 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.h28 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
29 SDValue Dst, SDValue Src,
30 SDValue Size, unsigned Align,
35 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL,
36 SDValue Chain, SDValue Dst, SDValue Byte,
37 SDValue Size, unsigned Align, bool IsVolatile,
40 std::pair<SDValue, SDValue>
41 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
42 SDValue Src1, SDValue Src2, SDValue Size,
46 std::pair<SDValue, SDValue>
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DSystemZISelLowering.h224 void LowerAsmOperandForConstraint(SDValue Op,
226 std::vector<SDValue> &Ops,
231 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
234 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
238 SmallVectorImpl<SDValue> &InVals) const override;
239 SDValue LowerCall(CallLoweringInfo &CLI,
240 SmallVectorImpl<SDValue> &InVals) const override;
242 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
244 const SmallVectorImpl<SDValue> &OutVals,
246 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
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DSystemZSelectionDAGInfo.cpp32 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, in emitMemMem()
33 unsigned Loop, SDValue Chain, SDValue Dst, in emitMemMem()
34 SDValue Src, uint64_t Size) { in emitMemMem()
55 SDValue SystemZSelectionDAGInfo::
56 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in EmitTargetCodeForMemcpy()
57 SDValue Dst, SDValue Src, SDValue Size, unsigned Align, in EmitTargetCodeForMemcpy()
62 return SDValue(); in EmitTargetCodeForMemcpy()
67 return SDValue(); in EmitTargetCodeForMemcpy()
73 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in memsetStore()
74 SDValue Dst, uint64_t ByteVal, uint64_t Size, in memsetStore()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h209 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
228 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
232 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
263 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
280 bool isZExtFree(SDValue Val, EVT VT2) const override;
339 SDValue
340 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
343 SmallVectorImpl<SDValue> &InVals) const override;
345 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
346 SmallVectorImpl<SDValue> &InVals) const override;
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.h27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
35 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
38 bool isHWTrueValue(SDValue Op) const;
39 bool isHWFalseValue(SDValue Op) const;
44 virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
48 SmallVectorImpl<SDValue> &InVals) const;
50 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
53 const SmallVectorImpl<SDValue> &OutVals,
56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDGPUISelLowering.h27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
35 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
38 bool isHWTrueValue(SDValue Op) const;
39 bool isHWFalseValue(SDValue Op) const;
44 virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
48 SmallVectorImpl<SDValue> &InVals) const;
50 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
53 const SmallVectorImpl<SDValue> &OutVals,
56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/ARM/
DARMISelLowering.h239 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
244 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
264 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
265 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
282 bool isZExtFree(SDValue Val, EVT VT2) const override;
307 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
314 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
315 SDValue &Offset, ISD::MemIndexedMode &AM,
318 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
342 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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DARMISelDAGToDAG.cpp86 inline SDValue getI32Imm(unsigned Imm) { in getI32Imm()
94 bool isShifterOpProfitable(const SDValue &Shift,
96 bool SelectRegShifterOperand(SDValue N, SDValue &A,
97 SDValue &B, SDValue &C,
99 bool SelectImmShifterOperand(SDValue N, SDValue &A,
100 SDValue &B, bool CheckProfitability = true);
101 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A, in SelectShiftRegShifterOperand()
102 SDValue &B, SDValue &C) { in SelectShiftRegShifterOperand()
106 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A, in SelectShiftImmShifterOperand()
107 SDValue &B) { in SelectShiftImmShifterOperand()
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.h76 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
82 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/X86/
DX86ISelLowering.h502 bool isZeroNode(SDValue Elt);
533 SDValue getPICJumpTableRelocBase(SDValue Table,
576 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
581 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
585 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
597 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
614 void computeKnownBitsForTargetNode(const SDValue Op,
622 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
629 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
648 void LowerAsmOperandForConstraint(SDValue Op,
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/external/llvm/lib/Target/Sparc/
DSparcISelLowering.h58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
63 void computeKnownBitsForTargetNode(const SDValue Op,
79 void LowerAsmOperandForConstraint(SDValue Op,
81 std::vector<SDValue> &Ops,
92 SDValue
93 LowerFormalArguments(SDValue Chain,
98 SmallVectorImpl<SDValue> &InVals) const override;
99 SDValue LowerFormalArguments_32(SDValue Chain,
104 SmallVectorImpl<SDValue> &InVals) const;
105 SDValue LowerFormalArguments_64(SDValue Chain,
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h84 IsEligibleForTailCallOptimization(SDValue Callee,
91 const SmallVectorImpl<SDValue> &OutVals,
100 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
103 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerFormalArguments(SDValue Chain,
112 SmallVectorImpl<SDValue> &InVals) const override;
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DHexagonISelDAGToDAG.cpp68 inline bool foldGlobalAddress(SDValue &N, SDValue &R);
69 inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
70 bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
71 bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
72 bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
73 bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
74 bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
75 bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
76 bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
77 bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h53 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
55 std::vector<SDValue> &OutOps) override;
77 inline SDValue getI32Imm(unsigned Imm) { in getI32Imm()
82 bool SelectDirectAddr(SDValue N, SDValue &Address);
84 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
85 SDValue &Offset, MVT mvt);
86 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 SDValue &Offset);
88 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 SDValue &Offset);
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