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Searched refs:SIGN_EXTEND (Results 1 – 25 of 39) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp569 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, in getCastInstrCost()
571 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, in getCastInstrCost()
573 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
575 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, in getCastInstrCost()
577 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost()
579 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
581 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
583 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, in getCastInstrCost()
596 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, in getCastInstrCost()
598 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, in getCastInstrCost()
[all …]
DX86ISelLowering.cpp870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand); in resetOperationActions()
1212 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); in resetOperationActions()
1213 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in resetOperationActions()
1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
1395 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in resetOperationActions()
1396 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in resetOperationActions()
1397 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom); in resetOperationActions()
1398 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom); in resetOperationActions()
1399 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
1576 setTargetDAGCombine(ISD::SIGN_EXTEND); in resetOperationActions()
[all …]
DX86FastISel.cpp1046 ISD::SIGN_EXTEND; in X86SelectRet()
2859 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
2883 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp215 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
217 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
223 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
225 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
227 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
229 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
231 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
363 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 }, in getCastInstrCost()
DARMISelLowering.cpp555 setTargetDAGCombine(ISD::SIGN_EXTEND); in ARMTargetLowering()
1459 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
3768 CastOpc = ISD::SIGN_EXTEND; in LowerVectorINT_TO_FP()
5662 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) in isSignExtended()
5747 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) in SkipExtensionForVMULL()
5886 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
5887 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); in LowerSDIV_v4i8()
5916 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
5917 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); in LowerSDIV_v4i16()
5958 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); in LowerSDIV()
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-AnInfiniteLoopInDAGCombine.ll10 ; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h359 SIGN_EXTEND, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp856 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1234 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); in visit()
1311 case ISD::SIGN_EXTEND: in combine()
1642 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADD()
1644 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
2241 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
2242 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
2359 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); in visitSMUL_LOHI()
2360 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); in visitSMUL_LOHI()
2459 N0.getOpcode() == ISD::SIGN_EXTEND || in SimplifyBinOpWithSameOpcodeHands()
[all …]
DLegalizeFloatTypes.cpp601 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in SoftenFloatRes_XINT_TO_FP()
1194 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP()
1202 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP()
1206 Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src); in ExpandFloatRes_XINT_TO_FP()
DLegalizeVectorTypes.cpp95 case ISD::SIGN_EXTEND: in ScalarizeVectorResult()
409 case ISD::SIGN_EXTEND: in ScalarizeVectorOperand()
618 case ISD::SIGN_EXTEND: in SplitVectorResult()
1220 case ISD::SIGN_EXTEND: in SplitVectorOperand()
1610 case ISD::SIGN_EXTEND: in WidenVectorResult()
2405 case ISD::SIGN_EXTEND: in WidenVectorOperand()
2491 case ISD::SIGN_EXTEND: in WidenVecOp_EXTEND()
DLegalizeVectorOps.cpp271 case ISD::SIGN_EXTEND: in LegalizeOp()
399 ISD::SIGN_EXTEND; in PromoteINT_TO_FP()
DSelectionDAGDumper.cpp220 case ISD::SIGN_EXTEND: return "sign_extend"; in getOperationName()
DLegalizeIntegerTypes.cpp95 case ISD::SIGN_EXTEND: in PromoteIntegerResult()
318 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant()
428 if (N->getOpcode() == ISD::SIGN_EXTEND) in PromoteIntRes_INT_EXTEND()
825 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; in PromoteIntegerOperand()
1146 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult()
2174 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); in ExpandIntRes_SIGN_EXTEND()
DSelectionDAG.cpp241 return ISD::SIGN_EXTEND; in getExtForLoadExtType()
1005 getNode(ISD::SIGN_EXTEND, DL, VT, Op) : in getSExtOrTrunc()
2177 case ISD::SIGN_EXTEND: { in computeKnownBits()
2384 case ISD::SIGN_EXTEND: in ComputeNumSignBits()
2676 case ISD::SIGN_EXTEND: in getNode()
2793 case ISD::SIGN_EXTEND: in getNode()
2803 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) in getNode()
2837 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
2863 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
DFastISel.cpp302 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, in getRegForGEPIndex()
1178 return SelectCast(I, ISD::SIGN_EXTEND); in SelectOperator()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering()
198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering()
DSIISelLowering.cpp424 && Arg0.getOpcode() == ISD::SIGN_EXTEND in PerformDAGCombine()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand); in InitAMDILLowering()
198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering()
DSIISelLowering.cpp424 && Arg0.getOpcode() == ISD::SIGN_EXTEND in PerformDAGCombine()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp851 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul()
877 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) { in SelectMul()
1031 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) { in SelectTruncate()
1057 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) { in SelectTruncate()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp115 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); in MSP430TargetLowering()
196 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); in LowerOperation()
612 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp514 if (IndexOpcode == ISD::SIGN_EXTEND || in shouldUseLA()
780 case ISD::SIGN_EXTEND: { in expandRxSBG()
DSystemZISelLowering.cpp297 setTargetDAGCombine(ISD::SIGN_EXTEND); in SystemZTargetLowering()
654 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1270 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND) in shouldSwapCmpOperands()
1719 (Pos.getOpcode() == ISD::SIGN_EXTEND && in isAbsolute()
2035 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0), in lowerSMUL_LOHI()
2098 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0); in lowerSDIVREM()
2535 if (Opcode == ISD::SIGN_EXTEND) { in PerformDAGCombine()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp649 setTargetDAGCombine(ISD::SIGN_EXTEND); in PPCTargetLowering()
4080 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
4509 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin()
4791 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerReturn()
5252 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64, in LowerINT_TO_FP()
7447 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND && in DAGCombineTruncBoolExt()
7459 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND && in DAGCombineTruncBoolExt()
7469 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND || in DAGCombineTruncBoolExt()
7500 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND || in DAGCombineTruncBoolExt()
7512 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND || in DAGCombineTruncBoolExt()
[all …]
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1284 ExtendKind = ISD::SIGN_EXTEND; in GetReturnInfo()
1369 case SExt: return ISD::SIGN_EXTEND; in InstructionOpcodeToISD()

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