| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 210 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
213 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
225 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized. in getArithmeticInstrCost()
226 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized. in getArithmeticInstrCost()
227 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized. in getArithmeticInstrCost()
269 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
270 { ISD::SRA, MVT::v8i16, 1 }, // psraw. in getArithmeticInstrCost()
271 { ISD::SRA, MVT::v4i32, 1 }, // psrad. in getArithmeticInstrCost()
325 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized. in getArithmeticInstrCost()
326 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized. in getArithmeticInstrCost()
[all …]
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-09.ll | 45 ; Check that we use SRAK over SRA where useful.
55 ; Check that we use SRA over SRAK where possible.
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| D | shift-03.ll | 5 ; Check the low end of the SRA range.
14 ; Check the high end of the defined SRA range.
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| D | shift-10.ll | 69 ; Test that SRA gets replaced with SRL if the sign bit is the only one
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| /external/llvm/test/CodeGen/X86/ |
| D | pr14204.ll | 4 ; SLL/SRA.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 76 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
600 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt); in PromoteIntRes_SRA()
835 case ISD::SRA: in PromoteIntegerOperand()
1207 case ISD::SRA: in ExpandIntegerResult()
1384 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
1386 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1389 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1391 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1395 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1403 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); in ExpandShiftByConstant()
[all …]
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| D | LegalizeVectorOps.cpp | 254 case ISD::SRA: in LegalizeOp()
550 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); in ExpandLoad()
724 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || in ExpandSEXTINREG()
737 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
781 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
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| D | DAGCombiner.cpp | 980 if (Opc == ISD::SRA) in PromoteIntShiftOp()
1221 case ISD::SRA: return visitSRA(N); in visit()
1307 case ISD::SRA: in combine()
2026 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, in visitSDIV()
2039 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD, in visitSDIV() local
2045 return SRA; in visitSDIV()
2047 AddToWorkList(SRA.getNode()); in visitSDIV()
2048 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA); in visitSDIV()
2227 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0, in visitMULHS()
2482 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && in SimplifyBinOpWithSameOpcodeHands()
[all …]
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| D | FastISel.cpp | 417 ISDOpcode = ISD::SRA; in SelectBinaryOp()
1127 return SelectBinaryOp(I, ISD::SRA); in SelectOperator()
1299 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) && in FastEmit_ri_()
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| /external/valgrind/main/none/tests/mips64/ |
| D | shift_instructions.c | 10 SRA, SRAV, SRL, SRLV enumerator
177 case SRA: in main()
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| /external/chromium_org/v8/src/mips/ |
| D | constants-mips.cc | 226 case SRA: in InstructionType()
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| D | constants-mips.h | 321 SRA = ((0 << 3) + 3), enumerator
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| D | disasm-mips.cc | 633 case SRA: in DecodeTypeRegister()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 92 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
95 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
189 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
752 case ISD::SRA: in LowerShifts()
753 return DAG.getNode(MSP430ISD::SRA, dl, in LowerShifts()
972 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
1159 case MSP430ISD::SRA: return "MSP430ISD::SRA"; in getTargetNodeName()
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| D | MSP430ISelLowering.h | 65 SHL, SRA, SRL enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| D | memcpy.S | 112 #define SRA dsra macro
149 #define SRA sra macro
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 1089 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; in LowerSRXParts() local
1104 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
1108 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
1109 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
1590 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount); in LowerLOAD()
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| D | AMDGPUISelLowering.cpp | 296 setOperationAction(ISD::SRA, VT, Expand); in AMDGPUTargetLowering()
1301 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT)); in LowerSDIV24()
1728 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
1827 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift); in ExpandSIGN_EXTEND_INREG()
2015 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, in PerformDAGCombine()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
512 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT)); in LowerSDIV24()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
512 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT)); in LowerSDIV24()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 818 case ISD::SRA: { in expandRxSBG()
828 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { in expandRxSBG()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 95 SRL, SRA, SHL, enumerator
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 297 case ISD::SRA: in getShiftTypeForNode()
1431 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && in isBitfieldExtractOpFromShr()
1485 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMWri : AArch64::UBFMWri; in isBitfieldExtractOpFromShr()
1487 Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri; in isBitfieldExtractOpFromShr()
1507 case ISD::SRA: in isBitfieldExtractOp()
2080 case ISD::SRA: in Select()
|