| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| D | Execution.cpp | 51 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
54 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst() argument
65 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst() argument
76 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst() argument
87 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst() argument
98 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst() argument
102 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
105 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
115 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
120 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 197 unsigned Src1 = 0, SubReg1; in isProfitableToTransform() local
215 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
216 if (Src1) in isProfitableToTransform()
220 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1)) in isProfitableToTransform()
290 unsigned Src1 = 0, SubReg1; in transformInstruction() local
308 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1); in transformInstruction()
311 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1)) { in transformInstruction()
312 assert(Src1 && "Can't delete copy w/o a valid original source!"); in transformInstruction()
324 if (!Src1) { in transformInstruction()
326 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | R600ExpandSpecialInstrs.cpp | 98 unsigned Src1 = 0; in runOnMachineFunction() local
102 Src1 = MI.getOperand(2).getReg(); in runOnMachineFunction()
107 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
153 .addReg(Src1) in runOnMachineFunction()
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| D | R600Instructions.td | 805 // Src1 = Offset
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600ExpandSpecialInstrs.cpp | 98 unsigned Src1 = 0; in runOnMachineFunction() local
102 Src1 = MI.getOperand(2).getReg(); in runOnMachineFunction()
107 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
153 .addReg(Src1) in runOnMachineFunction()
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| D | R600Instructions.td | 805 // Src1 = Offset
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| /external/llvm/lib/Target/R600/ |
| D | R600ExpandSpecialInstrs.cpp | 224 unsigned Src1 = BMI->getOperand( in runOnMachineFunction() local
228 (void) Src1; in runOnMachineFunction()
230 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
231 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
275 unsigned Src1 = 0; in runOnMachineFunction() local
281 Src1 = MI.getOperand(Src1Idx).getReg(); in runOnMachineFunction()
287 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
292 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
327 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 635 const MachineOperand &Src1 = MI->getOperand(Src1Idx); in verifyInstruction() local
636 if (Src1.isImm() || Src1.isFPImm()) { in verifyInstruction()
664 const MachineOperand &Src1 = MI->getOperand(3); in verifyInstruction() local
666 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) { in verifyInstruction()
667 if (!compareMachineOp(Src0, Src1) && in verifyInstruction()
868 MachineOperand &Src1 = MI->getOperand(Src1Idx); in legalizeOperands() local
879 if (ReadsVCC && Src1.isReg() && in legalizeOperands()
880 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { in legalizeOperands()
887 if (Src1.isImm() || Src1.isFPImm() || in legalizeOperands()
888 (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) { in legalizeOperands()
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| D | R600InstrInfo.cpp | 1277 MachineOperand &Src1 = MI->getOperand( in buildSlotOfVectorInstruction() local
1280 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg()); in buildSlotOfVectorInstruction()
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| D | EvergreenInstructions.td | 261 // Src1 = Offset
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 159 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
161 EVT PtrVT = Src1.getValueType(); in emitCLC()
171 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
174 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
193 SDValue Src1, SDValue Src2, SDValue Size, in EmitTargetCodeForMemcmp() argument
199 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
249 SDValue Src1, SDValue Src2, in EmitTargetCodeForStrcmp() argument
252 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::Other, MVT::Glue); in EmitTargetCodeForStrcmp()
253 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()
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| D | SystemZSelectionDAGInfo.h | 42 SDValue Src1, SDValue Src2, SDValue Size,
60 SDValue Src1, SDValue Src2,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 160 MachineOperand &Src1 = MI->getOperand(1); in runOnMachineFunction() local
162 if (Src1.getImm() != 0) in runOnMachineFunction()
177 MachineOperand &Src1 = MI->getOperand(1); in runOnMachineFunction() local
182 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction()
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| D | HexagonISelDAGToDAG.cpp | 1329 SDNode* Src1 = N->getOperand(0).getNode(); in SelectAdd() local
1330 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse() in SelectAdd()
1331 || Src1->getValueType(0) != MVT::i32) { in SelectAdd()
1339 Src1->getOperand(0), in SelectAdd()
1340 Src1->getOperand(1)); in SelectAdd()
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| /external/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 307 const MachineOperand &Src1 = MI->getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM() local
311 .addOperand(Src1) in processInstructionForSLM()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1008 unsigned Src1 = MI->getOperand(1).getReg(); in printArithExtend() local
1009 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) && in printArithExtend()
1011 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) && in printArithExtend()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 3078 SDValue Src1 = getValue(I.getOperand(0)); in visitShuffleVector() local
3087 EVT SrcVT = Src1.getValueType(); in visitShuffleVector()
3091 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
3107 VT, Src1, Src2)); in visitShuffleVector()
3115 VT, Src2, Src1)); in visitShuffleVector()
3122 bool Src1U = Src1.getOpcode() == ISD::UNDEF; in visitShuffleVector()
3128 MOps1[0] = Src1; in visitShuffleVector()
3131 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
3145 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, in visitShuffleVector()
3201 SDValue &Src = Input == 0 ? Src1 : Src2; in visitShuffleVector()
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| D | LegalizeVectorTypes.cpp | 1250 SDValue Src1 = N->getOperand(2); in SplitVecOp_VSELECT() local
1266 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL); in SplitVecOp_VSELECT()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2675 SDValue Src1 = Op.getOperand(0); in LowerADDC_ADDE_SUBC_SUBE() local
2676 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
2677 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 7082 unsigned Src1 = MI->getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
7097 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2); in EmitInstrWithCustomInserter()
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