| /external/llvm/lib/Target/R600/ |
| D | SILowerI1Copies.cpp | 113 const TargetRegisterClass *SrcRC = in runOnMachineFunction() local
117 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { in runOnMachineFunction()
130 SrcRC == &AMDGPU::VReg_1RegClass) { in runOnMachineFunction()
|
| D | SIFixSGPRCopies.cpp | 185 const TargetRegisterClass *SrcRC; in isVGPRToSGPRCopy() local
192 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg); in isVGPRToSGPRCopy()
193 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
|
| D | SIInstrInfo.cpp | 1494 const TargetRegisterClass *SrcRC = Src.isReg() ? in splitScalar64BitBCNT() local
1501 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
1503 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, in splitScalar64BitBCNT()
1505 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, in splitScalar64BitBCNT()
|
| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 455 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
458 if (DefRC == SrcRC) in shareSameRegisterFile()
464 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
470 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
475 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
477 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
569 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src); in optimizeCopyOrBitcast() local
572 ShouldRewrite = shareSameRegisterFile(TRI, DefRC, DefSubReg, SrcRC, in optimizeCopyOrBitcast()
|
| D | RegisterCoalescer.cpp | 290 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
299 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
306 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
310 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
313 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
328 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
146 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>;
151 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>;
156 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
|
| D | MipsInstrInfo.td | 880 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
881 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
882 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
891 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
892 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
893 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
|
| D | MipsDSPInstrInfo.td | 1279 RegisterClass SrcRC> :
1280 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1281 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 40 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
42 if (DestRC != SrcRC) in copyPhysReg()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrMMX.td | 178 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
181 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
182 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>,
189 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
193 (ins DstRC:$src1, SrcRC:$src2), asm,
194 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
|
| D | X86InstrAVX512.td | 371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
406 (ins KRC:$mask, SrcRC:$src),
2913 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2916 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2985 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2989 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2991 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
[all …]
|
| D | X86InstrSSE.td | 1477 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1480 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1481 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1488 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1492 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1500 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1503 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1637 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1640 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1642 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
[all …]
|
| D | X86FastISel.cpp | 1053 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); in X86SelectRet() local
1055 if (!SrcRC->contains(DstReg)) in X86SelectRet()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 390 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
393 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
398 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()
|
| D | InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg()
171 if (MatchReg && SrcRC->getCopyCost() < 0) { in EmitCopyFromReg()
|
| D | ScheduleDAGRRList.cpp | 1139 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
1142 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
1147 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1931 const TargetRegisterClass *SrcRC = in processBlock() local
1938 unsigned NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2134 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); in SelectRet() local
2136 if (!SrcRC->contains(DstReg)) in SelectRet()
|