| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 215 unsigned SuperReg = *SRI; in uniqueSuperReg() local
218 return SuperReg; in uniqueSuperReg()
247 unsigned SuperReg = uniqueSuperReg(Reg, TRI); in spillCalleeSavedRegisters() local
253 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); in spillCalleeSavedRegisters()
254 CanUseDblStore = (SuperRegNext == SuperReg); in spillCalleeSavedRegisters()
259 TII.storeRegToStackSlot(MBB, MI, SuperReg, true, in spillCalleeSavedRegisters()
261 MBB.addLiveIn(SuperReg); in spillCalleeSavedRegisters()
302 unsigned SuperReg = uniqueSuperReg(Reg, TRI); in restoreCalleeSavedRegisters() local
307 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); in restoreCalleeSavedRegisters()
308 CanUseDblLoad = (SuperRegNext == SuperReg); in restoreCalleeSavedRegisters()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 560 unsigned SuperReg = 0; in FindSuitableFreeRegisters() local
563 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
564 SuperReg = Reg; in FindSuitableFreeRegisters()
583 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
584 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
597 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << in FindSuitableFreeRegisters()
611 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); in FindSuitableFreeRegisters()
634 if (NewSuperReg == SuperReg) continue; in FindSuitableFreeRegisters()
645 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
648 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
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| D | ScheduleDAGInstrs.cpp | 1090 const unsigned SuperReg = MO.getReg(); in toggleKillFlag() local
1092 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) { in toggleKillFlag()
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.h | 30 MachineOperand &SuperReg,
36 MachineOperand &SuperReg,
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| D | SIInstrInfo.cpp | 780 MachineOperand &SuperReg, in buildExtractSubReg() argument
785 assert(SuperReg.isReg()); in buildExtractSubReg()
796 .addOperand(SuperReg); in buildExtractSubReg()
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| D | R600InstrInfo.cpp | 1096 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index); in reserveIndirectRegisters() local
1097 Reserved.set(SuperReg); in reserveIndirectRegisters()
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| D | SIISelLowering.cpp | 470 unsigned SuperReg = MI->getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
486 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg) in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 698 unsigned SuperReg = in copyPhysReg() local
701 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
704 DestReg = SuperReg; in copyPhysReg()
707 unsigned SuperReg = in copyPhysReg() local
710 if (VSXSelfCopyCrash && SrcReg == SuperReg) in copyPhysReg()
713 DestReg = SuperReg; in copyPhysReg()
716 unsigned SuperReg = in copyPhysReg() local
719 if (VSXSelfCopyCrash && DestReg == SuperReg) in copyPhysReg()
722 SrcReg = SuperReg; in copyPhysReg()
725 unsigned SuperReg = in copyPhysReg() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1891 SDValue SuperReg = SDValue(VLd, 0); in SelectVLD() local
1897 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2124 SDValue SuperReg; in SelectVLDSTLane() local
2129 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
2131 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2138 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2140 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2142 Ops.push_back(SuperReg); in SelectVLDSTLane()
2156 SuperReg = SDValue(VLdLn, 0); in SelectVLDSTLane()
2162 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1005 SDValue SuperReg = SDValue(Ld, 0); in SelectLoad() local
1008 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1036 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoad() local
1038 ReplaceUses(SDValue(N, 0), SuperReg); in SelectPostLoad()
1042 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1152 SDValue SuperReg = SDValue(Ld, 0); in SelectLoadLane() local
1158 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1204 SDValue SuperReg = SDValue(Ld, 1); in SelectPostLoadLane() local
1207 Narrow ? NarrowVector(SuperReg, *CurDAG) : SuperReg); in SelectPostLoadLane()
1214 SuperReg); in SelectPostLoadLane()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5556 unsigned SuperReg = MRI->getMatchingSuperReg( in ParseInstruction() local
5559 assert(SuperReg && "expected register pair"); in ParseInstruction()
5561 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); in ParseInstruction()
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