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Searched refs:TB (Results 1 – 25 of 74) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrSystem.td19 TB;
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
54 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
55 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
56 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
60 IIC_SYS_ENTER_EXIT>, TB;
63 IIC_SYS_ENTER_EXIT>, TB;
[all …]
DX86InstrSVM.td19 def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
22 def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
25 def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
29 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
34 "vmrun\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
37 "vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
42 "vmload\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
45 "vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
50 "vmsave\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
53 "vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
[all …]
DX86InstrExtension.td45 TB, OpSize16, Sched<[WriteALU]>;
49 TB, OpSize16, Sched<[WriteALULd]>;
53 [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB,
57 [(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB,
61 [(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB,
66 OpSize32, TB, Sched<[WriteALULd]>;
71 TB, OpSize16, Sched<[WriteALU]>;
75 TB, OpSize16, Sched<[WriteALULd]>;
79 [(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB,
83 [(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB,
[all …]
DX86InstrVMX.td33 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
37 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
39 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
41 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
45 "vmptrst\t$vmcs", []>, TB;
63 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
DX86InstrCMovSetCC.td25 IIC_CMOV16_RR>, TB, OpSize16;
31 IIC_CMOV32_RR>, TB, OpSize32;
37 IIC_CMOV32_RR>, TB;
47 TB, OpSize16;
53 TB, OpSize32;
58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
88 IIC_SET_R>, TB, Sched<[WriteALU]>;
92 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
DX86InstrTSX.td31 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
35 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
DX86InstrInfo.td915 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
917 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
1055 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1059 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1415 OpSize16, TB;
1419 OpSize32, TB;
1422 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1436 >, OpSize16, TB, Requires<[FastBTMem]>;
1442 >, OpSize32, TB, Requires<[FastBTMem]>;
1448 >, TB;
[all …]
DX86InstrShiftRotate.td696 TB, OpSize16;
702 TB, OpSize16;
707 IIC_SHD32_REG_CL>, TB, OpSize32;
712 IIC_SHD32_REG_CL>, TB, OpSize32;
718 TB;
724 TB;
734 TB, OpSize16;
741 TB, OpSize16;
748 TB, OpSize32;
755 TB, OpSize32;
[all …]
/external/clang/test/CXX/special/class.dtor/
Dp3-0x.cpp66 struct TB { struct
67 ~TB() throw(int);
72 TB<T> b;
114 TB<T> b;
/external/chromium_org/tools/clang/blink_gc_plugin/tests/
Dvirtual_and_trace_after_dispatch.h17 enum Type { TB }; enumerator
25 B() : A(TB) { } in B()
Dfinalize_after_dispatch.cpp14 case TB: in trace()
33 case TB: in finalizeGarbageCollectedObject()
Dtrace_after_dispatch.h17 enum Type { TB, TC, TD }; enumerator
25 B() : A(TB) { } in B()
Dfinalize_after_dispatch.h39 enum Type { TB, TC, TD }; enumerator
47 B() : A(TB) { } in B()
Dvirtual_and_trace_after_dispatch.cpp14 case TB: in trace()
Dtrace_after_dispatch.cpp14 case TB: in trace()
/external/llvm/lib/Target/Hexagon/
DHexagonHardwareLoops.cpp373 MachineBasicBlock *TB = nullptr, *FB = nullptr; in findInductionRegister() local
374 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false); in findInductionRegister()
481 MachineBasicBlock *TB = nullptr, *FB = nullptr; in getLoopTripCount() local
482 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false); in getLoopTripCount()
490 assert (TB && "Latch block without a branch?"); in getLoopTripCount()
491 assert ((!FB || TB == Header || FB == Header) && "Branches not to header?"); in getLoopTripCount()
492 if (!TB || (FB && TB != Header && FB != Header)) in getLoopTripCount()
499 bool Negated = (Cond.size() > 1) ^ (TB != Header); in getLoopTripCount()
1295 MachineBasicBlock *TB = nullptr, *FB = nullptr; in fixupInductionVariable() local
1298 bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false); in fixupInductionVariable()
[all …]
/external/qemu/docs/
DCPU-EMULATION.TXT11 Each fragment is translated into a "translated block" (a.k.a. TB) of host
13 instruction pointer changes (i.e. at the end of TB execution), a hash
14 table lookup is performed to find the next TB to execute.
17 sometimes possible to 'link' the end of a given TB to the start of
21 (described below in "MMU emulation"), there are actually two TB caches per
33 into a TB. This is done by decomposing each instruction into a series of
/external/llvm/test/CodeGen/X86/
Disel-sink2.ll10 br i1 %T, label %TB, label %F
11 TB:
/external/clang/test/SemaCXX/
Dvirtual-override.cpp225 template <int N> struct TB {}; struct
226 struct D : public TB<0> {};
230 virtual TB<N>* f2(); // expected-note{{overridden virtual function is here}}
/external/chromium_org/ipc/
Dipc_message_macros.h467 template<class T, class S, class P, typename TA, typename TB> \
469 void (T::*func)(P*, TA, TB)) { \
479 template<class T, class S, class P, typename TA, typename TB, typename TC> \
481 void (T::*func)(P*, TA, TB, TC)) { \
491 template<class T, class S, class P, typename TA, typename TB, typename TC, \
494 void (T::*func)(P*, TA, TB, TC, TD)) { \
504 template<class T, class S, class P, typename TA, typename TB, typename TC, \
507 void (T::*func)(P*, TA, TB, TC, TD, TE)) { \
545 template<typename TA, typename TB> \
546 static void WriteReplyParams(Message* reply, TA a, TB b) { \
[all …]
Dipc_message_utils.h931 template<typename TA, typename TB>
932 static void WriteReplyParams(Message* reply, TA a, TB b) {
937 template<typename TA, typename TB, typename TC>
938 static void WriteReplyParams(Message* reply, TA a, TB b, TC c) {
943 template<typename TA, typename TB, typename TC, typename TD>
944 static void WriteReplyParams(Message* reply, TA a, TB b, TC c, TD d) {
949 template<typename TA, typename TB, typename TC, typename TD, typename TE>
950 static void WriteReplyParams(Message* reply, TA a, TB b, TC c, TD d, TE e) {
/external/antlr/antlr-3.4/tool/src/main/resources/org/antlr/tool/templates/dot/
Ddecision-rank.st1 {rank=same; rankdir=TB; <states; separator="; ">}
/external/mesa3d/src/gallium/drivers/nv50/
Dnv50_formats.c165 F3A(R8G8B8X8_UNORM, RGBX8_UNORM, C0, C1, C2, xx, UNORM, 8_8_8_8, TB),
166 C4A(R8G8B8A8_SRGB, RGBA8_SRGB, C0, C1, C2, C3, UNORM, 8_8_8_8, TB, 0),
180 C4B(B5G5R5A1_UNORM, BGR5_A1_UNORM, C2, C1, C0, C3, UNORM, 5_5_5_1, TB),
181 F3B(B5G5R5X1_UNORM, BGR5_X1_UNORM, C2, C1, C0, xx, UNORM, 5_5_5_1, TB),
193 F3B(R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT, 11_11_10, TB),
195 F3B(L8_UNORM, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
196 F3B(L8_SRGB, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
202 F3B(L16_FLOAT, R16_FLOAT, C0, C0, C0, xx, FLOAT, 16, TB),
205 F3B(L32_FLOAT, R32_FLOAT, C0, C0, C0, xx, FLOAT, 32, TB),
222 A1B(A8_UNORM, A8_UNORM, xx, xx, xx, C0, UNORM, 8, TB),
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/
Dnv50_formats.c165 F3A(R8G8B8X8_UNORM, RGBX8_UNORM, C0, C1, C2, xx, UNORM, 8_8_8_8, TB),
166 C4A(R8G8B8A8_SRGB, RGBA8_SRGB, C0, C1, C2, C3, UNORM, 8_8_8_8, TB, 0),
180 C4B(B5G5R5A1_UNORM, BGR5_A1_UNORM, C2, C1, C0, C3, UNORM, 5_5_5_1, TB),
181 F3B(B5G5R5X1_UNORM, BGR5_X1_UNORM, C2, C1, C0, xx, UNORM, 5_5_5_1, TB),
193 F3B(R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT, 11_11_10, TB),
195 F3B(L8_UNORM, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
196 F3B(L8_SRGB, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
202 F3B(L16_FLOAT, R16_FLOAT, C0, C0, C0, xx, FLOAT, 16, TB),
205 F3B(L32_FLOAT, R32_FLOAT, C0, C0, C0, xx, FLOAT, 32, TB),
222 A1B(A8_UNORM, A8_UNORM, xx, xx, xx, C0, UNORM, 8, TB),
/external/qemu/tcg/
DTODO9 - Move the slow part of the qemu_ld/st ops after the end of the TB.

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