| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 40 UXTB, enumerator
60 case AArch64_AM::UXTB: return "uxtb"; in getShiftExtendName()
127 case 0: return AArch64_AM::UXTB; in getExtendType()
154 case AArch64_AM::UXTB: return 0; break; in getExtendEncoding()
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| /external/chromium_org/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 141 COMPARE(Mov(w10, Operand(w11, UXTB)), "uxtb w10, w11"); in TEST_()
142 COMPARE(Mov(x12, Operand(x13, UXTB, 1)), "ubfiz x12, x13, #1, #8"); in TEST_()
376 COMPARE(add(w0, w1, Operand(w2, UXTB)), "add w0, w1, w2, uxtb"); in TEST_()
377 COMPARE(adds(x3, x4, Operand(w5, UXTB, 1)), "adds x3, x4, w5, uxtb #1"); in TEST_()
386 COMPARE(cmn(w0, Operand(w1, UXTB, 2)), "cmn w0, w1, uxtb #2"); in TEST_()
389 COMPARE(add(w0, wcsp, Operand(w1, UXTB)), "add w0, wcsp, w1, uxtb"); in TEST_()
402 COMPARE(sub(w0, w1, Operand(w2, UXTB)), "sub w0, w1, w2, uxtb"); in TEST_()
403 COMPARE(subs(x3, x4, Operand(w5, UXTB, 1)), "subs x3, x4, w5, uxtb #1"); in TEST_()
415 COMPARE(sub(w0, wcsp, Operand(w1, UXTB)), "sub w0, wcsp, w1, uxtb"); in TEST_()
|
| D | test-assembler-arm64.cc | 305 __ Mvn(w10, Operand(w2, UXTB)); in TEST()
378 __ Mov(w23, Operand(w13, UXTB)); in TEST()
556 __ Orr(w6, w0, Operand(w1, UXTB)); in TEST()
648 __ Orn(w6, w0, Operand(w1, UXTB)); in TEST()
717 __ And(w6, w0, Operand(w1, UXTB)); in TEST()
858 __ Bic(w6, w0, Operand(w1, UXTB)); in TEST()
986 __ Eor(w6, w0, Operand(w1, UXTB)); in TEST()
1055 __ Eon(w6, w0, Operand(w1, UXTB)); in TEST()
3449 __ Add(x10, x0, Operand(x1, UXTB, 0)); in TEST()
3450 __ Add(x11, x0, Operand(x1, UXTB, 1)); in TEST()
[all …]
|
| /external/vixl/test/ |
| D | test-disasm-a64.cc | 117 COMPARE(Mov(w10, Operand(w11, UXTB)), "uxtb w10, w11"); in TEST()
118 COMPARE(Mov(x12, Operand(x13, UXTB, 1)), "ubfiz x12, x13, #1, #8"); in TEST()
338 COMPARE(add(w0, w1, Operand(w2, UXTB)), "add w0, w1, w2, uxtb"); in TEST()
339 COMPARE(adds(x3, x4, Operand(w5, UXTB, 1)), "adds x3, x4, w5, uxtb #1"); in TEST()
348 COMPARE(cmn(w0, Operand(w1, UXTB, 2)), "cmn w0, w1, uxtb #2"); in TEST()
351 COMPARE(add(w0, wsp, Operand(w1, UXTB)), "add w0, wsp, w1, uxtb"); in TEST()
364 COMPARE(sub(w0, w1, Operand(w2, UXTB)), "sub w0, w1, w2, uxtb"); in TEST()
365 COMPARE(subs(x3, x4, Operand(w5, UXTB, 1)), "subs x3, x4, w5, uxtb #1"); in TEST()
377 COMPARE(sub(w0, wsp, Operand(w1, UXTB)), "sub w0, wsp, w1, uxtb"); in TEST()
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| D | test-assembler-a64.cc | 270 __ Mvn(w10, Operand(w2, UXTB)); in TEST()
436 __ Mov(w23, Operand(w13, UXTB)); in TEST()
521 __ Orr(w6, w0, Operand(w1, UXTB)); in TEST()
610 __ Orn(w6, w0, Operand(w1, UXTB)); in TEST()
677 __ And(w6, w0, Operand(w1, UXTB)); in TEST()
815 __ Bic(w6, w0, Operand(w1, UXTB)); in TEST()
939 __ Eor(w6, w0, Operand(w1, UXTB)); in TEST()
1006 __ Eon(w6, w0, Operand(w1, UXTB)); in TEST()
2972 __ Add(x10, x0, Operand(x1, UXTB, 0)); in TEST()
2973 __ Add(x11, x0, Operand(x1, UXTB, 1)); in TEST()
[all …]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 521 # UXTB/UXTH
|
| D | basic-arm-instructions.txt | 2368 # UXTB
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| D | thumb2.txt | 2632 # UXTB
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
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| D | basic-arm-instructions.s | 2885 @ UXTB
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| D | basic-thumb2-instructions.s | 3557 @ UXTB
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 458 UXTB, enumerator
|
| /external/vixl/src/a64/ |
| D | constants-a64.h | 232 UXTB = 0, enumerator
|
| D | assembler-a64.cc | 1785 case UXTB: in EmitExtendShift()
|
| D | simulator-a64.cc | 335 case UXTB: in ExtendValue()
|
| /external/chromium_org/v8/src/arm64/ |
| D | constants-arm64.h | 340 UXTB = 0, enumerator
|
| D | assembler-arm64.cc | 2152 case UXTB: in EmitExtendShift()
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| D | simulator-arm64.cc | 912 case UXTB: in ExtendValue()
|
| D | macro-assembler-arm64.cc | 2326 Cmp(input.W(), Operand(input.W(), UXTB)); in ClampInt32ToUint8()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 161 // EXAMPLE: ADDXre Xn, Xm, UXTB #1
|
| D | AArch64ISelDAGToDAG.cpp | 364 return AArch64_AM::UXTB; in getExtendTypeForNode()
382 return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend; in getExtendTypeForNode()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 951 return (ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB || in isExtend()
2285 .Case("uxtb", AArch64_AM::UXTB) in tryParseOptionalShiftExtend()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2893 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
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| D | ARMScheduleSwift.td | 1194 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
|
| D | ARMInstrInfo.td | 3294 def UXTB : AI_ext_rrot<0b01101110,
5323 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5448 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
|