| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 43 UXTX, enumerator
63 case AArch64_AM::UXTX: return "uxtx"; in getShiftExtendName()
130 case 3: return AArch64_AM::UXTX; in getExtendType()
157 case AArch64_AM::UXTX: return 3; break; in getExtendEncoding()
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| /external/vixl/src/a64/ |
| D | disasm-a64.cc | 155 const char *form = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
157 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
1627 (instr->ExtendMode() == UXTX))) { in SubstituteExtendField()
1660 if (!((ext == UXTX) && (shift == 0))) { in SubstituteLSRegOffsetField()
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| D | assembler-a64.cc | 235 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); in Operand()
266 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
1791 case UXTX: in EmitExtendShift()
1864 ext = UXTX; in LoadStore()
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| D | macro-assembler-a64.cc | 199 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in LogicalMacro()
703 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in AddSubWithCarryMacro()
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| D | constants-a64.h | 235 UXTX = 3, enumerator
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| D | simulator-a64.cc | 353 case UXTX: in ExtendValue()
764 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
|
| /external/chromium_org/v8/src/arm64/ |
| D | disasm-arm64.cc | 148 const char *form = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
150 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
1633 (instr->ExtendMode() == UXTX))) { in SubstituteExtendField()
1666 if (!((ext == UXTX) && (shift == 0))) { in SubstituteLSRegOffsetField()
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| D | assembler-arm64-inl.h | 361 ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
392 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
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| D | constants-arm64.h | 343 UXTX = 3, enumerator
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| D | assembler-arm64.cc | 2158 case UXTX: in EmitExtendShift()
2232 ext = UXTX; in LoadStore()
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| D | simulator-arm64.cc | 930 case UXTX: in ExtendValue()
1453 ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | macro-assembler-arm64.cc | 139 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in LogicalMacro()
484 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in AddSubWithCarryMacro()
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1006 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1010 ExtType == AArch64_AM::UXTX) || in printArithExtend()
|
| /external/chromium_org/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 380 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4"); in TEST_()
392 COMPARE(cmn(csp, Operand(xzr, UXTX, 3)), "cmn csp, xzr, lsl #3"); in TEST_()
406 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4"); in TEST_()
418 COMPARE(cmp(csp, Operand(xzr, UXTX, 3)), "cmp csp, xzr, lsl #3"); in TEST_()
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| D | test-assembler-arm64.cc | 559 __ Orr(x9, x0, Operand(x1, UXTX, 3)); in TEST()
651 __ Orn(x9, x0, Operand(x1, UXTX, 3)); in TEST()
720 __ And(x9, x0, Operand(x1, UXTX, 3)); in TEST()
861 __ Bic(x9, x0, Operand(x1, UXTX, 3)); in TEST()
989 __ Eor(x9, x0, Operand(x1, UXTX, 3)); in TEST()
1058 __ Eon(x9, x0, Operand(x1, UXTX, 3)); in TEST()
3886 __ Adc(x13, x1, Operand(x2, UXTX, 4)); in TEST()
3898 __ Adc(x23, x1, Operand(x2, UXTX, 4)); in TEST()
7990 __ adds(xzr, x0, Operand(x1, UXTX)); in TEST()
7991 __ adds(xzr, x1, Operand(xzr, UXTX)); in TEST()
[all …]
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| /external/vixl/test/ |
| D | test-disasm-a64.cc | 342 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4"); in TEST()
354 COMPARE(cmn(sp, Operand(xzr, UXTX, 3)), "cmn sp, xzr, lsl #3"); in TEST()
368 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4"); in TEST()
380 COMPARE(cmp(sp, Operand(xzr, UXTX, 3)), "cmp sp, xzr, lsl #3"); in TEST()
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| D | test-assembler-a64.cc | 524 __ Orr(x9, x0, Operand(x1, UXTX, 3)); in TEST()
613 __ Orn(x9, x0, Operand(x1, UXTX, 3)); in TEST()
680 __ And(x9, x0, Operand(x1, UXTX, 3)); in TEST()
818 __ Bic(x9, x0, Operand(x1, UXTX, 3)); in TEST()
942 __ Eor(x9, x0, Operand(x1, UXTX, 3)); in TEST()
1009 __ Eon(x9, x0, Operand(x1, UXTX, 3)); in TEST()
3395 __ Adc(x13, x1, Operand(x2, UXTX, 4)); in TEST()
3407 __ Adc(x23, x1, Operand(x2, UXTX, 4)); in TEST()
7377 __ adds(xzr, x0, Operand(x1, UXTX)); in TEST()
7378 __ adds(xzr, x1, Operand(xzr, UXTX)); in TEST()
[all …]
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 954 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtend()
964 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX; in isExtend64()
970 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtendLSL64()
1531 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX; in addExtend64Operands()
2288 .Case("uxtx", AArch64_AM::UXTX) in tryParseOptionalShiftExtend()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 461 UXTX, enumerator
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1099 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val); in isScaledAddr()
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| D | AArch64InstrFormats.td | 1667 // UXTX and SXTX only.
1686 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1689 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1732 // UXTX and SXTX only.
1776 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
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| D | AArch64ISelDAGToDAG.cpp | 566 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX); in SelectArithExtendedRegister()
|