/external/llvm/test/CodeGen/Mips/ |
D | divrem.ll | 88 ; ACC32: divu $zero, $4, $5 91 ; ACC64: divu $zero, $4, $5 94 ; GPR32: divu $2, $4, $5 97 ; GPR64: divu $2, $4, $5 114 ; ACC32: divu $zero, $4, $5 117 ; ACC64: divu $zero, $4, $5 182 ; ACC32: divu $zero, $4, $5 189 ; ACC64: divu $zero, $4, $5 200 ; GPR32-DAG: divu $2, $4, $5 208 ; GPR64-DAG: divu $2, $4, $5 [all …]
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D | divu.ll | 12 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
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D | remu.ll | 13 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
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D | divu_remu.ll | 16 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
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/external/llvm/test/MC/Mips/ |
D | micromips-alu-instructions.s | 40 # CHECK-EL: divu $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xbb] 74 # CHECK-EB: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c] 106 divu $0, $9, $7
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/external/chromium_org/v8/test/cctest/ |
D | test-disasm-mips.cc | 134 COMPARE(divu(a0, a1), in TEST() 136 COMPARE(divu(t2, t3), in TEST() 138 COMPARE(divu(v0, v1), in TEST()
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/external/llvm/test/MC/Mips/mips32r6/ |
D | invalid-mips1.s | 24 # divu has been re-encoded. See valid.s
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D | invalid-mips2.s | 26 # divu has been re-encoded. See valid.s
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/external/llvm/test/MC/Mips/mips64r6/ |
D | invalid-mips2.s | 29 # divu has been re-encoded. See valid.s
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D | invalid-mips1.s | 27 # divu has been re-encoded. See valid.s
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D | invalid-mips3.s | 33 # divu has been re-encoded. See valid.s
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D | invalid-mips64.s | 54 # divu has been re-encoded. See valid.s
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/external/llvm/test/MC/Mips/mips1/ |
D | valid.s | 39 divu $zero,$25,$15
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/external/llvm/test/MC/Mips/mips2/ |
D | valid.s | 41 divu $zero,$25,$15
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/external/valgrind/main/none/tests/mips64/ |
D | arithmetic_instruction.stdout.exp-mips64 | 10223 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0 10224 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0 10225 divu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0 10226 divu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0 10227 divu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0 10228 divu $t0, $t1 :: rs 0x17c56b6b, rt 0xffffffffa6322bdf, HI 0x17c56b6b, LO 0x0 10229 divu $t0, $t1 :: rs 0x1a864db2, rt 0xffffffffab710d06, HI 0x1a864db2, LO 0x0 10230 divu $t0, $t1 :: rs 0x1e475005, rt 0xffffffffafb010b1, HI 0x1e475005, LO 0x0 10231 divu $t0, $t1 :: rs 0x2608edb8, rt 0xffffffff97ffad0c, HI 0x2608edb8, LO 0x0 10232 divu $t0, $t1 :: rs 0x22c9f00f, rt 0xffffffff933eb0bb, HI 0x22c9f00f, LO 0x0 [all …]
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D | arithmetic_instruction.stdout.exp-mips64r2 | 10223 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0 10224 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0 10225 divu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0 10226 divu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0 10227 divu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0 10228 divu $t0, $t1 :: rs 0x17c56b6b, rt 0xffffffffa6322bdf, HI 0x17c56b6b, LO 0x0 10229 divu $t0, $t1 :: rs 0x1a864db2, rt 0xffffffffab710d06, HI 0x1a864db2, LO 0x0 10230 divu $t0, $t1 :: rs 0x1e475005, rt 0xffffffffafb010b1, HI 0x1e475005, LO 0x0 10231 divu $t0, $t1 :: rs 0x2608edb8, rt 0xffffffff97ffad0c, HI 0x2608edb8, LO 0x0 10232 divu $t0, $t1 :: rs 0x22c9f00f, rt 0xffffffff933eb0bb, HI 0x22c9f00f, LO 0x0 [all …]
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/external/llvm/test/MC/Disassembler/Mips/ |
D | micromips.txt | 97 # CHECK-EB: divu $zero, $9, $7
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D | micromips_le.txt | 97 # CHECK: divu $zero, $9, $7
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D | mips32r6.txt | 86 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
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/external/llvm/test/MC/Mips/mips32/ |
D | valid.s | 47 divu $zero,$25,$15
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/external/llvm/test/MC/Mips/mips32r2/ |
D | valid.s | 50 divu $zero,$25,$15
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/external/llvm/test/MC/Mips/mips3/ |
D | valid.s | 58 divu $zero,$25,$15
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/external/llvm/test/MC/Mips/mips5/ |
D | valid.s | 60 divu $zero,$25,$15
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/external/llvm/test/MC/Mips/mips4/ |
D | valid.s | 60 divu $zero,$25,$15
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/external/llvm/test/MC/Mips/mips64/ |
D | valid.s | 65 divu $zero,$25,$15
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