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/external/llvm/test/MC/AArch64/
Darm64-bitfield-encoding.s34 extr w1, w2, w3, #15
35 extr x2, x3, x4, #1
37 ; CHECK: extr w1, w2, w3, #15 ; encoding: [0x41,0x3c,0x83,0x13]
38 ; CHECK: extr x2, x3, x4, #1 ; encoding: [0x62,0x04,0xc4,0x93]
Dbasic-a64-diagnostics.s1485 extr w2, w20, w30, #-1
1486 extr w9, w19, w20, #32
1494 extr x10, x15, x20, #-1
1495 extr x20, x25, x30, #64
Dbasic-a64-instructions.s1715 extr w3, w5, w7, #0
1716 extr w11, w13, w17, #31
1720 extr x3, x5, x7, #15
1721 extr x11, x13, x17, #63
/external/chromium_org/third_party/openssl/openssl/crypto/aes/asm/
Daes-ia64.S115 (p0) extr.u te22=s2,8,8 } // 0/0:s2>>8&0xff
121 (p0) extr.u te23=s3,8,8 } // 1/1:s3>>8&0xff
127 (p0) extr.u te20=s0,8,8 } // 2/2:s0>>8&0xff
133 (p0) extr.u te21=s1,8,8 } // 3/3:s1>>8&0xff
139 (p0) extr.u te11=s1,16,8 } // 4/0:s1>>16&0xff
145 (p0) extr.u te12=s2,16,8 } // 5/1:s2>>16&0xff
151 (p0) extr.u te10=s0,16,8 } // 6/3:s0>>16&0xff
199 extr.u te22=s2,8,8 } // 0/0:s2>>8&0xff
205 extr.u te23=s3,8,8 } // 1/1:s3>>8&0xff
211 extr.u te20=s0,8,8 } // 2/2:s0>>8&0xff
[all …]
/external/openssl/crypto/aes/asm/
Daes-ia64.S115 (p0) extr.u te22=s2,8,8 } // 0/0:s2>>8&0xff
121 (p0) extr.u te23=s3,8,8 } // 1/1:s3>>8&0xff
127 (p0) extr.u te20=s0,8,8 } // 2/2:s0>>8&0xff
133 (p0) extr.u te21=s1,8,8 } // 3/3:s1>>8&0xff
139 (p0) extr.u te11=s1,16,8 } // 4/0:s1>>16&0xff
145 (p0) extr.u te12=s2,16,8 } // 5/1:s2>>16&0xff
151 (p0) extr.u te10=s0,16,8 } // 6/3:s0>>16&0xff
199 extr.u te22=s2,8,8 } // 0/0:s2>>8&0xff
205 extr.u te23=s3,8,8 } // 1/1:s3>>8&0xff
211 extr.u te20=s0,8,8 } // 2/2:s0>>8&0xff
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-extract.ll1 ; RUN: llc -aarch64-extr-generation=true -verify-machineinstrs < %s \
29 ; CHECK: extr {{w[0-9]+}}, w0, w1, #26
41 ; CHECK: extr {{x[0-9]+}}, x0, x1, #40
54 ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
Dextract.ll28 ; CHECK: extr {{w[0-9]+}}, w0, w1, #26
40 ; CHECK: extr {{x[0-9]+}}, x0, x1, #40
53 ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
Darm64-andCmpBrToTBZ.ll2 ; ModuleID = 'and-cbz-extr-mr.bc'
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-bitfield.txt28 # CHECK: extr w1, w2, w3, #15
29 # CHECK: extr x2, x3, x4, #1
Dbasic-a64-instructions.txt1298 # CHECK: extr w3, w5, w7, #0
1299 # CHECK: extr w11, w13, w17, #31
1303 # CHECK: extr x3, x5, x7, #15
1304 # CHECK: extr x11, x13, x17, #63
/external/llvm/test/CodeGen/Mips/
Ddsp-r1.ll5 ; CHECK: extr.w
7 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
11 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
17 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
25 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
29 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
35 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
39 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
45 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
49 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
[all …]
/external/libunwind/src/ia64/
Dgetcontext.S112 extr.u rPOS = rPOS, 3, 6 // get NaT bitnr for r0 // I0
/external/oprofile/module/ia64/
DIA64minstate.h155 extr.u r16=rCRIPSR, 32, 2; \
/external/chromium_org/v8/test/cctest/
Dtest-disasm-arm64.cc559 COMPARE(extr(w0, w1, w2, 0), "extr w0, w1, w2, #0"); in TEST_()
560 COMPARE(extr(x3, x4, x5, 1), "extr x3, x4, x5, #1"); in TEST_()
561 COMPARE(extr(w6, w7, w8, 31), "extr w6, w7, w8, #31"); in TEST_()
562 COMPARE(extr(x9, x10, x11, 63), "extr x9, x10, x11, #63"); in TEST_()
563 COMPARE(extr(w12, w13, w13, 10), "ror w12, w13, #10"); in TEST_()
564 COMPARE(extr(x14, x15, x15, 42), "ror x14, x15, #42"); in TEST_()
/external/vixl/test/
Dtest-disasm-a64.cc529 COMPARE(extr(w0, w1, w2, 0), "extr w0, w1, w2, #0"); in TEST()
530 COMPARE(extr(x3, x4, x5, 1), "extr x3, x4, x5, #1"); in TEST()
531 COMPARE(extr(w6, w7, w8, 31), "extr w6, w7, w8, #31"); in TEST()
532 COMPARE(extr(x9, x10, x11, 63), "extr x9, x10, x11, #63"); in TEST()
533 COMPARE(extr(w12, w13, w13, 10), "ror w12, w13, #10"); in TEST()
534 COMPARE(extr(x14, x15, x15, 42), "ror x14, x15, #42"); in TEST()
/external/valgrind/main/none/tests/mips32/
Dmips32_dsp.stdout.exp-BE1267 extr.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000
1268 extr.w $t5, $ac0, 31 :: rt 0xffffffff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000
1269 extr.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000
1270 extr.w $t7, $ac2, 0 :: rt 0xffffffff ac2 0xffffffffffffffff size 0 DSPCtrl 0x00000000
1271 extr.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x00000000fffffffe size 1 DSPCtrl 0x00000000
1272 extr.w $t1, $ac0, 31 :: rt 0x00000001 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000
1273 extr.w $t2, $ac1, 17 :: rt 0x0000c000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000
1274 extr.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000
1275 extr.w $t4, $ac3, 12 :: rt 0x00440000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000000
1276 extr.w $t5, $ac0, 3 :: rt 0xefffffff ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x00800000
[all …]
Dmips32_dsp.stdout.exp-LE1267 extr.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000
1268 extr.w $t5, $ac0, 31 :: rt 0xffffffff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000
1269 extr.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000
1270 extr.w $t7, $ac2, 0 :: rt 0xffffffff ac2 0xffffffffffffffff size 0 DSPCtrl 0x00000000
1271 extr.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x00000000fffffffe size 1 DSPCtrl 0x00000000
1272 extr.w $t1, $ac0, 31 :: rt 0x00000001 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000
1273 extr.w $t2, $ac1, 17 :: rt 0x0000c000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000
1274 extr.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000
1275 extr.w $t4, $ac3, 12 :: rt 0x00440000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000000
1276 extr.w $t5, $ac0, 3 :: rt 0xefffffff ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x00800000
[all …]
/external/vixl/doc/
Dsupported-instructions.md384 ### extr ### subsection
388 void extr(const Register& rd,
/external/vixl/src/a64/
Dassembler-a64.h979 void extr(const Register& rd,
1025 extr(rd, rs, rs, shift); in ror()
Dmacro-assembler-a64.h528 extr(rd, rn, rm, lsb); in Extr()
Dassembler-a64.cc770 void Assembler::extr(const Register& rd, in extr() function in vixl::Assembler
/external/chromium_org/v8/src/arm64/
Dassembler-arm64.h1267 void extr(const Register& rd,
1313 extr(rd, rs, rs, shift); in ror()
Dmacro-assembler-arm64-inl.h523 extr(rd, rn, rm, lsb); in Extr()
/external/openssl/crypto/md5/asm/
Dmd5-ia64.S175 #define GETRW(dst, src, align) extr.u dst = src, 8 * align, 32 - 8 * align
/external/chromium_org/third_party/openssl/openssl/crypto/md5/asm/
Dmd5-ia64.S175 #define GETRW(dst, src, align) extr.u dst = src, 8 * align, 32 - 8 * align

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