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/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips5-wrong-error.s25 c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
32 mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips5-wrong-error.s25 c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
32 mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips5-wrong-error.s25 c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
32 mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips4/
Dinvalid-mips5-wrong-error.s25 c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
32 mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
36 movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips5-wrong-error.s28 … c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
34 … mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
38 … movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
39 … msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
43 … nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/clang/test/CXX/except/except.spec/
Dp3.cpp77 void f17();
78 void f17() noexcept(false);
/external/clang/test/CodeGen/
Dfunction-attributes.c105 __attribute__ ((returns_twice)) void f17(void);
107 f17(); in f18()
Dregparm-struct.c161 __attribute__((regparm(3))) struct s12 f17(int a, int b, int c);
164 f17(41, 42, 43); in g17()
/external/llvm/test/CodeGen/PowerPC/
Dvsx-spill.ll7 …~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f2…
22 …~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f2…
36 …~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f2…
/external/llvm/test/MC/ARM/
Dsymbol-variants.s59 .word f17(target2)
61 @CHECK: 44 R_ARM_TARGET2 f17
/external/valgrind/main/none/tests/ppc64/
Dtest_isa_2_06_part2.c49 register double f17 __asm__ ("fr17");
1031 __asm__ __volatile__ ("fctiduz. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiduz()
1033 __asm__ __volatile__ ("fctiduz %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiduz()
1039 __asm__ __volatile__ ("fctidu. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctidu()
1041 __asm__ __volatile__ ("fctidu %0, %1" : "=d" (f17) : "d" (f14)); in test_fctidu()
1047 __asm__ __volatile__ ("fctiwuz. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwuz()
1049 __asm__ __volatile__ ("fctiwuz %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwuz()
1055 __asm__ __volatile__ ("fctiwu. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwu()
1057 __asm__ __volatile__ ("fctiwu %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwu()
1668 result = f17; in test_fct_ops()
Dtest_dfp3.c33 register double f17 __asm__ ("fr17");
833 f17 = d0x; in test_dfp_quai_ops()
901 f17 = d1x; in test_dfp_qua_ops()
960 f17 = d0x; in test_dfp_rrnd_ops()
1042 f17 = d0x; in test_dfp_xiex_ops()
1119 f17 = d0x; in test_dfp_rint_ops()
1198 f17 = d1x; in test_dfp_cmp_ops()
Dtest_isa_2_06_part1.c46 register double f17 __asm__ ("fr17");
1261 __asm__ __volatile__ ("fcfids %0, %1" : "=f" (f17): "d" (f14)); in test_fcfids()
1266 __asm__ __volatile__ ("fcfidus %0, %1" : "=f" (f17): "d" (f14)); in test_fcfidus()
1271 __asm__ __volatile__ ("fcfidu %0, %1" : "=f" (f17): "d" (f14)); in test_fcfidu()
1974 res = f17; in test_p7_fpops()
1978 resd = f17; in test_p7_fpops()
/external/valgrind/main/none/tests/ppc32/
Dtest_isa_2_06_part2.c49 register double f17 __asm__ ("fr17");
1031 __asm__ __volatile__ ("fctiduz. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiduz()
1033 __asm__ __volatile__ ("fctiduz %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiduz()
1039 __asm__ __volatile__ ("fctidu. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctidu()
1041 __asm__ __volatile__ ("fctidu %0, %1" : "=d" (f17) : "d" (f14)); in test_fctidu()
1047 __asm__ __volatile__ ("fctiwuz. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwuz()
1049 __asm__ __volatile__ ("fctiwuz %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwuz()
1055 __asm__ __volatile__ ("fctiwu. %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwu()
1057 __asm__ __volatile__ ("fctiwu %0, %1" : "=d" (f17) : "d" (f14)); in test_fctiwu()
1668 result = f17; in test_fct_ops()
Dtest_dfp3.c33 register double f17 __asm__ ("fr17");
833 f17 = d0x; in test_dfp_quai_ops()
901 f17 = d1x; in test_dfp_qua_ops()
960 f17 = d0x; in test_dfp_rrnd_ops()
1042 f17 = d0x; in test_dfp_xiex_ops()
1119 f17 = d0x; in test_dfp_rint_ops()
1198 f17 = d1x; in test_dfp_cmp_ops()
Dtest_isa_2_06_part1.c46 register double f17 __asm__ ("fr17");
1261 __asm__ __volatile__ ("fcfids %0, %1" : "=f" (f17): "d" (f14)); in test_fcfids()
1266 __asm__ __volatile__ ("fcfidus %0, %1" : "=f" (f17): "d" (f14)); in test_fcfidus()
1271 __asm__ __volatile__ ("fcfidu %0, %1" : "=f" (f17): "d" (f14)); in test_fcfidu()
1974 res = f17; in test_p7_fpops()
1978 resd = f17; in test_p7_fpops()
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg.ll20 …f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{…
44 …f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{…
/external/compiler-rt/lib/builtins/ppc/
DsaveFP.S24 stfd f17,-120(r1)
DrestFP.S26 lfd f17,-120(r1)
/external/chromium_org/v8/test/mjsunit/harmony/
Dblock-let-crankshaft.js34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26,
119 function f17() { function
/external/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-fpxx.ll13 …},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f13},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{…
35 ; O32-FPXX-INV-NOT: sdc1 $f17,
/external/llvm/test/CodeGen/SystemZ/
Dinsert-05.ll191 define i64 @f17(i32 %a) {
192 ; CHECK-LABEL: f17:
202 ; Repeat f17 with the operands reversed.
/external/llvm/test/Bitcode/
Dattributes-3.3.ll103 define void @f17(i8 align 4)
104 ; CHECK: define void @f17(i8 align 4)
/external/llvm/test/CodeGen/X86/
D2009-08-12-badswitch.ll21 declare void @f17() nounwind readnone
135 call void @f17()
/external/clang/test/CodeGenCXX/
Daarch64-mangle-neon-vectors.cpp72 void f17(int32x4_t) {} in f17() function

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