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/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips32r2.s8 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
9 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips5.s8 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips32/
Dinvalid-mips32r2.s13 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
15 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
16 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
19 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
21 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
24 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
33 …swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s69 luxc1 $f19,$s6($s5)
78 madd.d $f18,$f19,$f26,$f20
79 madd.s $f1,$f31,$f19,$f25
106 msub.s $f12,$f19,$f10,$f16
125 nmadd.d $f18,$f9,$f14,$f19
128 nmsub.s $f1,$f24,$f19,$f4
181 swxc1 $f19,$12($k0)
/external/llvm/test/CodeGen/PowerPC/
Dvsx-spill.ll7 …f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f2…
22 …f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f2…
36 …f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f2…
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips32r2.s19 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
23 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
24 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
48 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
53 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
56 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
65 …swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips5-wrong-error.s15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
39 neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips4/
Dinvalid-mips64r2.s17 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
20 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
26 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
32 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips5-wrong-error.s15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
39 neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
Dinvalid-mips5.s8 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s17 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
19 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
22 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips5-wrong-error.s15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
39 neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
Dinvalid-mips5.s11 …luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
32 …swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips5-wrong-error.s15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
28 cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
39 neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips5-wrong-error.s18 … c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
31 … cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
41 … neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/valgrind/main/none/tests/ppc64/
Dtest_dfp2.c40 register double f19 __asm__ ("fr19");
487 double resx = f19; in test_dfp_one_arg_ops()
561 double resx = f19; in test_dfp_two_arg_ops()
626 double resx = f19; in test_dcffix_dcffixq()
Dtest_dfp3.c35 register double f19 __asm__ ("fr19");
846 double resx = f19; in test_dfp_quai_ops()
910 double resx = f19; in test_dfp_qua_ops()
975 double resx = f19; in test_dfp_rrnd_ops()
1054 double resx = f19; in test_dfp_xiex_ops()
1072 double resx = f19; in test_dfp_xiex_ops()
1131 double resx = f19; in test_dfp_rint_ops()
/external/valgrind/main/none/tests/ppc32/
Dtest_dfp2.c40 register double f19 __asm__ ("fr19");
487 double resx = f19; in test_dfp_one_arg_ops()
561 double resx = f19; in test_dfp_two_arg_ops()
626 double resx = f19; in test_dcffix_dcffixq()
Dtest_dfp3.c35 register double f19 __asm__ ("fr19");
846 double resx = f19; in test_dfp_quai_ops()
910 double resx = f19; in test_dfp_qua_ops()
975 double resx = f19; in test_dfp_rrnd_ops()
1054 double resx = f19; in test_dfp_xiex_ops()
1072 double resx = f19; in test_dfp_xiex_ops()
1131 double resx = f19; in test_dfp_rint_ops()
/external/llvm/test/MC/ARM/
Dsymbol-variants.s65 .word f19(prel31)
67 @CHECK: 4c R_ARM_PREL31 f19
/external/llvm/test/MC/Mips/mips5/
Dinvalid-mips64r2.s24 …madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
30 …msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
36 …nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s128 luxc1 $f19,$s6($s5)
138 madd.s $f1,$f31,$f19,$f25
166 msub.s $f12,$f19,$f10,$f16
186 nmsub.s $f1,$f24,$f19,$f4
245 swxc1 $f19,$12($k0)
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg.ll20 …},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{…
44 …},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{…
/external/compiler-rt/lib/builtins/ppc/
DsaveFP.S26 stfd f19,-104(r1)
DrestFP.S28 lfd f19,-104(r1)

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