| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-thumbv8.txt | 154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
|
| D | invalid-armv8.txt | 154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
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| /external/llvm/test/MC/Mips/mips1/ |
| D | invalid-mips2-wrong-error.s | 10 … ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| D | invalid-mips3-wrong-error.s | 11 … ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| D | invalid-mips4-wrong-error.s | 11 … ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 48 … ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
|
| /external/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 55 … ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
|
| /external/llvm/test/MC/ARM/ |
| D | diagnostics.s | 394 ldc2 p2, c8, [r1], { 256 }
395 ldc2 p2, c8, [r1], { -1 }
398 @ CHECK-ERRORS: ldc2 p2, c8, [r1], { 256 }
401 @ CHECK-ERRORS: ldc2 p2, c8, [r1], { -1 }
|
| D | basic-arm-instructions.s | 813 ldc2 p0, c8, [r1, #4]
814 ldc2 p1, c7, [r2]
815 ldc2 p2, c6, [r3, #-224]
816 ldc2 p3, c5, [r4, #-120]!
817 ldc2 p4, c4, [r5], #16
818 ldc2 p5, c3, [r6], #-72
852 ldc2 p2, c8, [r1], { 25 }
854 @ CHECK: ldc2 p0, c8, [r1, #4] @ encoding: [0x01,0x80,0x91,0xfd]
855 @ CHECK: ldc2 p1, c7, [r2] @ encoding: [0x00,0x71,0x92,0xfd]
856 @ CHECK: ldc2 p2, c6, [r3, #-224] @ encoding: [0x38,0x62,0x13,0xfd]
[all …]
|
| D | basic-thumb2-instructions.s | 666 ldc2 p0, c8, [r1, #4]
667 ldc2 p1, c7, [r2]
668 ldc2 p2, c6, [r3, #-224]
669 ldc2 p3, c5, [r4, #-120]!
670 ldc2 p4, c4, [r5], #16
671 ldc2 p5, c3, [r6], #-72
692 ldc2 p2, c8, [r1], { 25 }
694 @ CHECK: ldc2 p0, c8, [r1, #4] @ encoding: [0x91,0xfd,0x01,0x80]
695 @ CHECK: ldc2 p1, c7, [r2] @ encoding: [0x92,0xfd,0x00,0x71]
696 @ CHECK: ldc2 p2, c6, [r3, #-224] @ encoding: [0x13,0xfd,0x38,0x62]
[all …]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 62 … ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 97 … ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
|
| /external/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 99 … ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
|
| /external/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 99 … ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
|
| /external/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 104 … ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
|
| /external/llvm/test/MC/Mips/ |
| D | mips-fpu-instructions.s | 177 # CHECK: ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb]
212 ldc2 $11, 12($ra)
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 118 … ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
|
| /external/chromium_org/v8/src/arm/ |
| D | assembler-arm.h | 1075 void ldc2(Coprocessor coproc, CRegister crd, const MemOperand& src,
1077 void ldc2(Coprocessor coproc, CRegister crd, Register base, int option,
|
| D | assembler-arm.cc | 2057 void Assembler::ldc2(Coprocessor coproc, in ldc2() function in v8::internal::Assembler
2065 void Assembler::ldc2(Coprocessor coproc, in ldc2() function in v8::internal::Assembler
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 410 def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
|
| D | Mips32r6InstrInfo.td | 566 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3944 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">, Requires<[PreV8]>;
|
| D | ARMInstrInfo.td | 4877 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
|