1 /*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_ALL_H
20 #define CPU_ALL_H
21
22 #include "qemu-common.h"
23 #include "qemu/queue.h"
24 #include "qemu/thread.h"
25 #include "qemu/tls.h"
26 #include "exec/cpu-common.h"
27
28 /* some important defines:
29 *
30 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
31 * memory accesses.
32 *
33 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
34 * otherwise little endian.
35 *
36 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
37 *
38 * TARGET_WORDS_BIGENDIAN : same for target cpu
39 */
40
41 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
42 #define BSWAP_NEEDED
43 #endif
44
45 #ifdef BSWAP_NEEDED
46
tswap16(uint16_t s)47 static inline uint16_t tswap16(uint16_t s)
48 {
49 return bswap16(s);
50 }
51
tswap32(uint32_t s)52 static inline uint32_t tswap32(uint32_t s)
53 {
54 return bswap32(s);
55 }
56
tswap64(uint64_t s)57 static inline uint64_t tswap64(uint64_t s)
58 {
59 return bswap64(s);
60 }
61
tswap16s(uint16_t * s)62 static inline void tswap16s(uint16_t *s)
63 {
64 *s = bswap16(*s);
65 }
66
tswap32s(uint32_t * s)67 static inline void tswap32s(uint32_t *s)
68 {
69 *s = bswap32(*s);
70 }
71
tswap64s(uint64_t * s)72 static inline void tswap64s(uint64_t *s)
73 {
74 *s = bswap64(*s);
75 }
76
77 #else
78
tswap16(uint16_t s)79 static inline uint16_t tswap16(uint16_t s)
80 {
81 return s;
82 }
83
tswap32(uint32_t s)84 static inline uint32_t tswap32(uint32_t s)
85 {
86 return s;
87 }
88
tswap64(uint64_t s)89 static inline uint64_t tswap64(uint64_t s)
90 {
91 return s;
92 }
93
tswap16s(uint16_t * s)94 static inline void tswap16s(uint16_t *s)
95 {
96 }
97
tswap32s(uint32_t * s)98 static inline void tswap32s(uint32_t *s)
99 {
100 }
101
tswap64s(uint64_t * s)102 static inline void tswap64s(uint64_t *s)
103 {
104 }
105
106 #endif
107
108 #if TARGET_LONG_SIZE == 4
109 #define tswapl(s) tswap32(s)
110 #define tswapls(s) tswap32s((uint32_t *)(s))
111 #define bswaptls(s) bswap32s(s)
112 #else
113 #define tswapl(s) tswap64(s)
114 #define tswapls(s) tswap64s((uint64_t *)(s))
115 #define bswaptls(s) bswap64s(s)
116 #endif
117
118 /* CPU memory access without any memory or io remapping */
119
120 /*
121 * the generic syntax for the memory accesses is:
122 *
123 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
124 *
125 * store: st{type}{size}{endian}_{access_type}(ptr, val)
126 *
127 * type is:
128 * (empty): integer access
129 * f : float access
130 *
131 * sign is:
132 * (empty): for floats or 32 bit size
133 * u : unsigned
134 * s : signed
135 *
136 * size is:
137 * b: 8 bits
138 * w: 16 bits
139 * l: 32 bits
140 * q: 64 bits
141 *
142 * endian is:
143 * (empty): target cpu endianness or 8 bit access
144 * r : reversed target cpu endianness (not implemented yet)
145 * be : big endian (not implemented yet)
146 * le : little endian (not implemented yet)
147 *
148 * access_type is:
149 * raw : host memory access
150 * user : user mode access using soft MMU
151 * kernel : kernel mode access using soft MMU
152 */
153
154 /* target-endianness CPU memory access functions */
155 #if defined(TARGET_WORDS_BIGENDIAN)
156 #define lduw_p(p) lduw_be_p(p)
157 #define ldsw_p(p) ldsw_be_p(p)
158 #define ldl_p(p) ldl_be_p(p)
159 #define ldq_p(p) ldq_be_p(p)
160 #define ldfl_p(p) ldfl_be_p(p)
161 #define ldfq_p(p) ldfq_be_p(p)
162 #define stw_p(p, v) stw_be_p(p, v)
163 #define stl_p(p, v) stl_be_p(p, v)
164 #define stq_p(p, v) stq_be_p(p, v)
165 #define stfl_p(p, v) stfl_be_p(p, v)
166 #define stfq_p(p, v) stfq_be_p(p, v)
167 #else
168 #define lduw_p(p) lduw_le_p(p)
169 #define ldsw_p(p) ldsw_le_p(p)
170 #define ldl_p(p) ldl_le_p(p)
171 #define ldq_p(p) ldq_le_p(p)
172 #define ldfl_p(p) ldfl_le_p(p)
173 #define ldfq_p(p) ldfq_le_p(p)
174 #define stw_p(p, v) stw_le_p(p, v)
175 #define stl_p(p, v) stl_le_p(p, v)
176 #define stq_p(p, v) stq_le_p(p, v)
177 #define stfl_p(p, v) stfl_le_p(p, v)
178 #define stfq_p(p, v) stfq_le_p(p, v)
179 #endif
180
181 /* MMU memory access macros */
182
183 #if defined(CONFIG_USER_ONLY)
184 #include <assert.h>
185 #include "exec/user/abitypes.h"
186
187 /* On some host systems the guest address space is reserved on the host.
188 * This allows the guest address space to be offset to a convenient location.
189 */
190 #if defined(CONFIG_USE_GUEST_BASE)
191 extern unsigned long guest_base;
192 extern int have_guest_base;
193 extern unsigned long reserved_va;
194 #define GUEST_BASE guest_base
195 #define RESERVED_VA reserved_va
196 #else
197 #define GUEST_BASE 0ul
198 #define RESERVED_VA 0ul
199 #endif
200
201 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
202 #define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
203
204 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
205 #define h2g_valid(x) 1
206 #else
207 #define h2g_valid(x) ({ \
208 unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
209 (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
210 (!RESERVED_VA || (__guest < RESERVED_VA)); \
211 })
212 #endif
213
214 #define h2g_nocheck(x) ({ \
215 unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
216 (abi_ulong)__ret; \
217 })
218
219 #define h2g(x) ({ \
220 /* Check if given address fits target address space */ \
221 assert(h2g_valid(x)); \
222 h2g_nocheck(x); \
223 })
224
225 #define saddr(x) g2h(x)
226 #define laddr(x) g2h(x)
227
228 #else /* !CONFIG_USER_ONLY */
229 /* NOTE: we use double casts if pointers and target_ulong have
230 different sizes */
231 #define saddr(x) (uint8_t *)(intptr_t)(x)
232 #define laddr(x) (uint8_t *)(intptr_t)(x)
233 #endif
234
235 #define ldub_raw(p) ldub_p(laddr((p)))
236 #define ldsb_raw(p) ldsb_p(laddr((p)))
237 #define lduw_raw(p) lduw_p(laddr((p)))
238 #define ldsw_raw(p) ldsw_p(laddr((p)))
239 #define ldl_raw(p) ldl_p(laddr((p)))
240 #define ldq_raw(p) ldq_p(laddr((p)))
241 #define ldfl_raw(p) ldfl_p(laddr((p)))
242 #define ldfq_raw(p) ldfq_p(laddr((p)))
243 #define stb_raw(p, v) stb_p(saddr((p)), v)
244 #define stw_raw(p, v) stw_p(saddr((p)), v)
245 #define stl_raw(p, v) stl_p(saddr((p)), v)
246 #define stq_raw(p, v) stq_p(saddr((p)), v)
247 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
248 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
249
250
251 #if defined(CONFIG_USER_ONLY)
252
253 /* if user mode, no other memory access functions */
254 #define ldub(p) ldub_raw(p)
255 #define ldsb(p) ldsb_raw(p)
256 #define lduw(p) lduw_raw(p)
257 #define ldsw(p) ldsw_raw(p)
258 #define ldl(p) ldl_raw(p)
259 #define ldq(p) ldq_raw(p)
260 #define ldfl(p) ldfl_raw(p)
261 #define ldfq(p) ldfq_raw(p)
262 #define stb(p, v) stb_raw(p, v)
263 #define stw(p, v) stw_raw(p, v)
264 #define stl(p, v) stl_raw(p, v)
265 #define stq(p, v) stq_raw(p, v)
266 #define stfl(p, v) stfl_raw(p, v)
267 #define stfq(p, v) stfq_raw(p, v)
268
269 #define cpu_ldub_code(env1, p) ldub_raw(p)
270 #define cpu_ldsb_code(env1, p) ldsb_raw(p)
271 #define cpu_lduw_code(env1, p) lduw_raw(p)
272 #define cpu_ldsw_code(env1, p) ldsw_raw(p)
273 #define cpu_ldl_code(env1, p) ldl_raw(p)
274 #define cpu_ldq_code(env1, p) ldq_raw(p)
275
276 #define cpu_ldub_data(env, addr) ldub_raw(addr)
277 #define cpu_lduw_data(env, addr) lduw_raw(addr)
278 #define cpu_ldsw_data(env, addr) ldsw_raw(addr)
279 #define cpu_ldl_data(env, addr) ldl_raw(addr)
280 #define cpu_ldq_data(env, addr) ldq_raw(addr)
281
282 #define cpu_stb_data(env, addr, data) stb_raw(addr, data)
283 #define cpu_stw_data(env, addr, data) stw_raw(addr, data)
284 #define cpu_stl_data(env, addr, data) stl_raw(addr, data)
285 #define cpu_stq_data(env, addr, data) stq_raw(addr, data)
286
287 #define cpu_ldub_kernel(env, addr) ldub_raw(addr)
288 #define cpu_lduw_kernel(env, addr) lduw_raw(addr)
289 #define cpu_ldsw_kernel(env, addr) ldsw_raw(addr)
290 #define cpu_ldl_kernel(env, addr) ldl_raw(addr)
291 #define cpu_ldq_kernel(env, addr) ldq_raw(addr)
292
293 #define cpu_stb_kernel(env, addr, data) stb_raw(addr, data)
294 #define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
295 #define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
296 #define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
297
298 #define ldub_kernel(p) ldub_raw(p)
299 #define ldsb_kernel(p) ldsb_raw(p)
300 #define lduw_kernel(p) lduw_raw(p)
301 #define ldsw_kernel(p) ldsw_raw(p)
302 #define ldl_kernel(p) ldl_raw(p)
303 #define ldq_kernel(p) ldq_raw(p)
304 #define ldfl_kernel(p) ldfl_raw(p)
305 #define ldfq_kernel(p) ldfq_raw(p)
306 #define stb_kernel(p, v) stb_raw(p, v)
307 #define stw_kernel(p, v) stw_raw(p, v)
308 #define stl_kernel(p, v) stl_raw(p, v)
309 #define stq_kernel(p, v) stq_raw(p, v)
310 #define stfl_kernel(p, v) stfl_raw(p, v)
311 #define stfq_kernel(p, vt) stfq_raw(p, v)
312
313 #define cpu_ldub_data(env, addr) ldub_raw(addr)
314 #define cpu_lduw_data(env, addr) lduw_raw(addr)
315 #define cpu_ldl_data(env, addr) ldl_raw(addr)
316
317 #define cpu_stb_data(env, addr, data) stb_raw(addr, data)
318 #define cpu_stw_data(env, addr, data) stw_raw(addr, data)
319 #define cpu_stl_data(env, addr, data) stl_raw(addr, data)
320 #endif /* defined(CONFIG_USER_ONLY) */
321
322 /* page related stuff */
323
324 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
325 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
326 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
327 #ifdef TARGET_X86_64
328 #define TARGET_PTE_MASK 0x7fffffffffffULL
329 #endif
330
331 /* ??? These should be the larger of uintptr_t and target_ulong. */
332 extern uintptr_t qemu_real_host_page_size;
333 extern uintptr_t qemu_host_page_size;
334 extern uintptr_t qemu_host_page_mask;
335
336 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
337
338 /* same as PROT_xxx */
339 #define PAGE_READ 0x0001
340 #define PAGE_WRITE 0x0002
341 #define PAGE_EXEC 0x0004
342 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
343 #define PAGE_VALID 0x0008
344 /* original state of the write flag (used when tracking self-modifying
345 code */
346 #define PAGE_WRITE_ORG 0x0010
347 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
348 /* FIXME: Code that sets/uses this is broken and needs to go away. */
349 #define PAGE_RESERVED 0x0020
350 #endif
351
352 #if defined(CONFIG_USER_ONLY)
353 void page_dump(FILE *f);
354
355 typedef int (*walk_memory_regions_fn)(void *, abi_ulong,
356 abi_ulong, unsigned long);
357 int walk_memory_regions(void *, walk_memory_regions_fn);
358
359 int page_get_flags(target_ulong address);
360 void page_set_flags(target_ulong start, target_ulong end, int flags);
361 int page_check_range(target_ulong start, target_ulong len, int flags);
362 #endif
363
364 void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
365 GCC_FMT_ATTR(2, 3);
366
367 /* Flags for use in ENV->INTERRUPT_PENDING.
368
369 The numbers assigned here are non-sequential in order to preserve
370 binary compatibility with the vmstate dump. Bit 0 (0x0001) was
371 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
372 the vmstate dump. */
373
374 /* External hardware interrupt pending. This is typically used for
375 interrupts from devices. */
376 #define CPU_INTERRUPT_HARD 0x0002
377
378 /* Exit the current TB. This is typically used when some system-level device
379 makes some change to the memory mapping. E.g. the a20 line change. */
380 #define CPU_INTERRUPT_EXITTB 0x0004
381
382 /* Halt the CPU. */
383 #define CPU_INTERRUPT_HALT 0x0020
384
385 /* Debug event pending. */
386 #define CPU_INTERRUPT_DEBUG 0x0080
387
388 /* Several target-specific external hardware interrupts. Each target/cpu.h
389 should define proper names based on these defines. */
390 #define CPU_INTERRUPT_TGT_EXT_0 0x0008
391 #define CPU_INTERRUPT_TGT_EXT_1 0x0010
392 #define CPU_INTERRUPT_TGT_EXT_2 0x0040
393 #define CPU_INTERRUPT_TGT_EXT_3 0x0200
394 #define CPU_INTERRUPT_TGT_EXT_4 0x1000
395
396 /* Several target-specific internal interrupts. These differ from the
397 preceding target-specific interrupts in that they are intended to
398 originate from within the cpu itself, typically in response to some
399 instruction being executed. These, therefore, are not masked while
400 single-stepping within the debugger. */
401 #define CPU_INTERRUPT_TGT_INT_0 0x0100
402 #define CPU_INTERRUPT_TGT_INT_1 0x0400
403 #define CPU_INTERRUPT_TGT_INT_2 0x0800
404 #define CPU_INTERRUPT_TGT_INT_3 0x2000
405
406 /* First unused bit: 0x4000. */
407
408 /* The set of all bits that should be masked when single-stepping. */
409 #define CPU_INTERRUPT_SSTEP_MASK \
410 (CPU_INTERRUPT_HARD \
411 | CPU_INTERRUPT_TGT_EXT_0 \
412 | CPU_INTERRUPT_TGT_EXT_1 \
413 | CPU_INTERRUPT_TGT_EXT_2 \
414 | CPU_INTERRUPT_TGT_EXT_3 \
415 | CPU_INTERRUPT_TGT_EXT_4)
416
417 /* Breakpoint/watchpoint flags */
418 #define BP_MEM_READ 0x01
419 #define BP_MEM_WRITE 0x02
420 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
421 #define BP_STOP_BEFORE_ACCESS 0x04
422 #define BP_WATCHPOINT_HIT 0x08
423 #define BP_GDB 0x10
424 #define BP_CPU 0x20
425
426 int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
427 CPUBreakpoint **breakpoint);
428 int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
429 void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
430 void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
431 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
432 int flags, CPUWatchpoint **watchpoint);
433 int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
434 target_ulong len, int flags);
435 void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
436 void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
437
438 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
439 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
440 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
441
442 void cpu_single_step(CPUState *cpu, int enabled);
443
444 /* IO ports API */
445 #include "exec/ioport.h"
446
447 /* Return the physical page corresponding to a virtual one. Use it
448 only for debugging because no protection checks are done. Return -1
449 if no page found. */
450 hwaddr cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
451
452 /* memory API */
453
454 extern int phys_ram_fd;
455 extern ram_addr_t ram_size;
456
457 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
458 #define RAM_PREALLOC_MASK (1 << 0)
459
460 typedef struct RAMBlock {
461 uint8_t *host;
462 ram_addr_t offset;
463 ram_addr_t length;
464 uint32_t flags;
465 char idstr[256];
466 /* Reads can take either the iothread or the ramlist lock.
467 * Writes must take both locks.
468 */
469 QTAILQ_ENTRY(RAMBlock) next;
470 int fd;
471 } RAMBlock;
472
473 typedef struct RAMList {
474 QemuMutex mutex;
475 uint8_t *phys_dirty;
476 RAMBlock *mru_block;
477 QTAILQ_HEAD(ram, RAMBlock) blocks;
478 uint32_t version;
479 } RAMList;
480 extern RAMList ram_list;
481
482 extern const char *mem_path;
483 extern int mem_prealloc;
484
485 /* physical memory access */
486
487 /* Flags stored in the low bits of the TLB virtual address. These are
488 defined so that fast path ram access is all zeros. */
489 /* Zero if TLB entry is valid. */
490 #define TLB_INVALID_MASK (1 << 3)
491 /* Set if TLB entry references a clean RAM page. The iotlb entry will
492 contain the page physical address. */
493 #define TLB_NOTDIRTY (1 << 4)
494 /* Set if TLB entry is an IO callback. */
495 #define TLB_MMIO (1 << 5)
496
497 #define VGA_DIRTY_FLAG 0x01
498 #define CODE_DIRTY_FLAG 0x02
499 #define MIGRATION_DIRTY_FLAG 0x08
500
501 /* read dirty bit (return 0 or 1) */
cpu_physical_memory_is_dirty(ram_addr_t addr)502 static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
503 {
504 return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
505 }
506
cpu_physical_memory_get_dirty_flags(ram_addr_t addr)507 static inline int cpu_physical_memory_get_dirty_flags(ram_addr_t addr)
508 {
509 return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS];
510 }
511
cpu_physical_memory_get_dirty(ram_addr_t addr,int dirty_flags)512 static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
513 int dirty_flags)
514 {
515 return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
516 }
517
cpu_physical_memory_set_dirty(ram_addr_t addr)518 static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
519 {
520 ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
521 }
522
cpu_physical_memory_set_dirty_flags(ram_addr_t addr,int dirty_flags)523 static inline int cpu_physical_memory_set_dirty_flags(ram_addr_t addr,
524 int dirty_flags)
525 {
526 return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] |= dirty_flags;
527 }
528
cpu_physical_memory_mask_dirty_range(ram_addr_t start,int length,int dirty_flags)529 static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start,
530 int length,
531 int dirty_flags)
532 {
533 int i, mask, len;
534 uint8_t *p;
535
536 len = length >> TARGET_PAGE_BITS;
537 mask = ~dirty_flags;
538 p = ram_list.phys_dirty + (start >> TARGET_PAGE_BITS);
539 for (i = 0; i < len; i++) {
540 p[i] &= mask;
541 }
542 }
543
544 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
545 int dirty_flags);
546 void cpu_tlb_update_dirty(CPUArchState *env);
547
548 int cpu_physical_memory_set_dirty_tracking(int enable);
549
550 int cpu_physical_memory_get_dirty_tracking(void);
551
552 int cpu_physical_sync_dirty_bitmap(hwaddr start_addr,
553 hwaddr end_addr);
554
555 void dump_exec_info(FILE *f,
556 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
557
558 /* Coalesced MMIO regions are areas where write operations can be reordered.
559 * This usually implies that write operations are side-effect free. This allows
560 * batching which can make a major impact on performance when using
561 * virtualization.
562 */
563 void qemu_register_coalesced_mmio(hwaddr addr, ram_addr_t size);
564
565 void qemu_unregister_coalesced_mmio(hwaddr addr, ram_addr_t size);
566
567 void qemu_flush_coalesced_mmio_buffer(void);
568
569
570 /* profiling */
571 #ifdef CONFIG_PROFILER
profile_getclock(void)572 static inline int64_t profile_getclock(void)
573 {
574 return cpu_get_real_ticks();
575 }
576
577 extern int64_t qemu_time, qemu_time_start;
578 extern int64_t tlb_flush_time;
579 extern int64_t dev_time;
580 #endif
581
582 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
583 void *buf, int len, int is_write);
584
585 void cpu_inject_x86_mce(CPUArchState *cenv, int bank, uint64_t status,
586 uint64_t mcg_status, uint64_t addr, uint64_t misc);
587
588 #endif /* CPU_ALL_H */
589