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Searched refs:rotrv (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/MC/Mips/
Dmicromips-shift-instructions.s17 # CHECK-EL: rotrv $9, $6, $7 # encoding: [0xc7,0x00,0xd0,0x48]
28 # CHECK-EB: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
36 rotrv $9, $6, $7
Dmips64-alu-instructions.s18 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
46 rotrv $9, $6, $7
Dmips-alu-instructions.s20 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
51 rotrv $9, $6, $7
/external/llvm/test/CodeGen/Mips/
Drotate.ll4 ; CHECK: rotrv $2, $4
25 ; CHECK: rotrv $2, $4, $5
/external/chromium_org/v8/test/cctest/
Dtest-disasm-mips.cc279 COMPARE(rotrv(a0, a1, a2), in TEST()
281 COMPARE(rotrv(s0, s1, s2), in TEST()
283 COMPARE(rotrv(t2, t3, t4), in TEST()
285 COMPARE(rotrv(v0, v1, fp), in TEST()
/external/valgrind/main/none/tests/mips32/
DMIPS32int.stdout.exp-mips32r2-BE1048 rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
1049 rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1050 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1051 rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1052 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1053 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1054 rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1055 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1056 rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1057 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
DMIPS32int.stdout.exp-mips32r2-LE1048 rotrv $t0, $t1, $t2 :: rd 0x6282b24e rs 0x31415927, rt 0xffffffff
1049 rotrv $t0, $t1, $t2 :: rd 0x31415927 rs 0x31415927, rt 0xee00ee00
1050 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x000000ff
1051 rotrv $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
1052 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000001
1053 rotrv $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
1054 rotrv $t0, $t1, $t2 :: rd 0x00000001 rs 0x80000000, rt 0xffffffff
1055 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
1056 rotrv $t0, $t1, $t2 :: rd 0x7fffffff rs 0x7fffffff, rt 0x00000000
1057 rotrv $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x80000000
[all …]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s138 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
/external/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s26 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips32/
Dinvalid-mips32r2.s28 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s196 … rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
/external/llvm/test/MC/Mips/mips5/
Dinvalid-mips64r2.s40 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Disassembler/Mips/
Dmicromips.txt121 # CHECK: rotrv $9, $6, $7
Dmicromips_le.txt121 # CHECK: rotrv $9, $6, $7
Dmips32r2_le.txt338 # CHECK: rotrv $9, $6, $7
Dmips32r2.txt338 # CHECK: rotrv $9, $6, $7
/external/valgrind/main/none/tests/mips64/
Dshift_instructions.stdout.exp-mips64r219457 rotrv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4
19458 rotrv $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03
19459 rotrv $t0, $t1, $t2 :: rd 0x608edb82, rs 0x9823b6e, rt 0xffffffffb8757bda
19460 rotrv $t0, $t1, $t2 :: rd 0x36c86a19, rs 0xd4326d9, rt 0xffffffffbcb4666d
19461 rotrv $t0, $t1, $t2 :: rd 0xffffffffdc130476, rs 0x130476dc, rt 0xffffffffa2f33668
19462 rotrv $t0, $t1, $t2 :: rd 0x2f8ad6d6, rs 0x17c56b6b, rt 0xffffffffa6322bdf
19463 rotrv $t0, $t1, $t2 :: rd 0xffffffffc86a1936, rs 0x1a864db2, rt 0xffffffffab710d06
19464 rotrv $t0, $t1, $t2 :: rd 0xffffffffa8028f23, rs 0x1e475005, rt 0xffffffffafb010b1
19465 rotrv $t0, $t1, $t2 :: rd 0xffffffffdb82608e, rs 0x2608edb8, rt 0xffffffff97ffad0c
19466 rotrv $t0, $t1, $t2 :: rd 0x593e01e4, rs 0x22c9f00f, rt 0xffffffff933eb0bb
[all …]
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips32r2.s60 …rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/lib/Target/Mips/
DMicroMipsInstrInfo.td167 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
DMipsInstrInfo.td1120 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
/external/chromium_org/v8/src/mips/
Dassembler-mips.h684 void rotrv(Register rd, Register rt, Register rs);
Dassembler-mips.cc1320 void Assembler::rotrv(Register rd, Register rt, Register rs) { in rotrv() function in v8::internal::Assembler
Dmacro-assembler-mips.cc838 rotrv(rd, rs, rt.rm()); in Ror()