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Searched refs:setReg (Results 1 – 25 of 55) sorted by relevance

123

/external/llvm/lib/Target/Sparc/
DDelaySlotFiller.cpp382 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
421 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
455 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
456 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
DSparcRegisterInfo.cpp186 MI.getOperand(2).setReg(SrcOddReg); in eliminateFrameIndex()
199 MI.getOperand(0).setReg(DestOddReg); in eliminateFrameIndex()
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp258 MI->getOperand(0).setReg(PeepholeSrc); in runOnMachineFunction()
296 MI->getOperand(PR).setReg(POrig); in runOnMachineFunction()
319 Dst.setReg(Src.getReg()); in ChangeOpInto()
/external/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg)); in shortenIIF()
/external/llvm/lib/CodeGen/
DAntiDepBreaker.h65 MI->getOperand(0).setReg(NewReg); in UpdateDbgValue()
DTargetInstrInfo.cpp165 MI->getOperand(0).setReg(Reg0); in commuteInstruction()
168 MI->getOperand(Idx2).setReg(Reg1); in commuteInstruction()
169 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
229 MO.setReg(Pred[j].getReg()); in PredicateInstruction()
DMachineRegisterInfo.cpp293 O.setReg(ToReg); in replaceRegWith()
430 UseMI->getOperand(0).setReg(0U); in markUsesInDebugValueAsUndef()
DSpiller.cpp124 mop.setReg(NewVReg); in trivialSpillEverywhere()
DTailDuplication.cpp443 MO.setReg(NewReg); in DuplicateInstruction()
450 MO.setReg(VI->second); in DuplicateInstruction()
516 II->getOperand(Idx).setReg(SrcReg); in UpdateSuccessorsPHIs()
528 II->getOperand(Idx).setReg(Reg); in UpdateSuccessorsPHIs()
DRegAllocFast.cpp671 MO.setReg(PhysReg); in setPhysReg()
676 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); in setPhysReg()
859 MO.setReg(0); in AllocateBasicBlock()
DMachineSSAUpdater.cpp232 U.setReg(NewVR); in RewriteUse()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DR600InstrInfo.cpp427 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
430 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
462 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
DAMDILCFGStructurizer.cpp1696 RegiT setReg) { in mergeLoopbreakBlock() argument
1722 if (exitBlk == exitLandBlk && setReg == INVALIDREGNUM) { in mergeLoopbreakBlock()
1741 if (setReg != INVALIDREGNUM) { in mergeLoopbreakBlock()
1742 CFGTraits::insertAssignInstrBefore(branchInstrPos, passRep, setReg, 1); in mergeLoopbreakBlock()
1765 RegiT setReg) { in settleLoopcontBlock() argument
1792 (setReg == INVALIDREGNUM && (&*contingBlk->rbegin()) == branchInstr); in settleLoopcontBlock()
1802 if (setReg != INVALIDREGNUM) { in settleLoopcontBlock()
1803 CFGTraits::insertAssignInstrBefore(branchInstrPos, passRep, setReg, 1); in settleLoopcontBlock()
1826 if (setReg != INVALIDREGNUM) { in settleLoopcontBlock()
1827 CFGTraits::insertAssignInstrBefore(contingBlk, passRep, setReg, 1); in settleLoopcontBlock()
/external/mesa3d/src/gallium/drivers/radeon/
DR600InstrInfo.cpp427 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
430 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
462 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
DAMDILCFGStructurizer.cpp1696 RegiT setReg) { in mergeLoopbreakBlock() argument
1722 if (exitBlk == exitLandBlk && setReg == INVALIDREGNUM) { in mergeLoopbreakBlock()
1741 if (setReg != INVALIDREGNUM) { in mergeLoopbreakBlock()
1742 CFGTraits::insertAssignInstrBefore(branchInstrPos, passRep, setReg, 1); in mergeLoopbreakBlock()
1765 RegiT setReg) { in settleLoopcontBlock() argument
1792 (setReg == INVALIDREGNUM && (&*contingBlk->rbegin()) == branchInstr); in settleLoopcontBlock()
1802 if (setReg != INVALIDREGNUM) { in settleLoopcontBlock()
1803 CFGTraits::insertAssignInstrBefore(branchInstrPos, passRep, setReg, 1); in settleLoopcontBlock()
1826 if (setReg != INVALIDREGNUM) { in settleLoopcontBlock()
1827 CFGTraits::insertAssignInstrBefore(contingBlk, passRep, setReg, 1); in settleLoopcontBlock()
/external/llvm/lib/Target/Mips/
DMipsOptimizePICCall.cpp138 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
229 getCallTargetRegOpnd(*I)->setReg(getReg(Entry)); in visitNode()
/external/llvm/lib/Target/R600/
DR600EmitClauseMarkers.cpp164 Consts[i].first->setReg( in SubstituteKCacheBank()
168 Consts[i].first->setReg( in SubstituteKCacheBank()
DR600InstrInfo.cpp988 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
991 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
1025 .setReg(Pred[2].getReg()); in PredicateInstruction()
1027 .setReg(Pred[2].getReg()); in PredicateInstruction()
1029 .setReg(Pred[2].getReg()); in PredicateInstruction()
1031 .setReg(Pred[2].getReg()); in PredicateInstruction()
1039 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
1301 .setReg(MO.getReg()); in buildSlotOfVectorInstruction()
DR600ExpandSpecialInstrs.cpp87 DstOp.setReg(AMDGPU::OQAP); in runOnMachineFunction()
93 Mov->getOperand(MovPredSelIdx).setReg( in runOnMachineFunction()
DSIInstrInfo.cpp981 MI->getOperand(i).setReg(DstReg); in legalizeOperands()
997 MI->getOperand(1).setReg(NewSrc0); in legalizeOperands()
1100 MI->getOperand(VAddrIdx).setReg(NewVAddr); in legalizeOperands()
1102 MI->getOperand(SRsrcIdx).setReg(NewSRsrc); in legalizeOperands()
1164 MI->getOperand(2).setReg(MI->getOperand(1).getReg()); in moveSMRDToVALU()
1168 MI->getOperand(1).setReg(SRsrc); in moveSMRDToVALU()
/external/llvm/lib/Target/AArch64/
DAArch64DeadRegisterDefinitionsPass.cpp110 MO.setReg(NewReg); in processMachineBasicBlock()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp286 MI->getOperand(0).setReg(Reg2); in commuteInstruction()
289 MI->getOperand(2).setReg(Reg1); in commuteInstruction()
290 MI->getOperand(1).setReg(Reg2); in commuteInstruction()
1052 UseMI->getOperand(UseIdx).setReg(ZeroReg); in FoldImmediate()
1745 MI->getOperand(0).setReg(KilledProdReg); in processBlock()
1746 MI->getOperand(1).setReg(KilledProdReg); in processBlock()
1747 MI->getOperand(3).setReg(AddReg); in processBlock()
1748 MI->getOperand(2).setReg(OtherProdReg); in processBlock()
1782 UseMO.setReg(KilledProdReg); in processBlock()
1948 SrcMO.setReg(NewVReg); in processBlock()
[all …]
/external/llvm/include/llvm/MC/
DMCInst.h69 void setReg(unsigned Reg) { in setReg() function
/external/libcxxabi/src/Unwind/
DUnwindCursor.hpp373 virtual void setReg(int, unw_word_t) = 0;
401 virtual void setReg(int, unw_word_t);
564 void UnwindCursor<A, R>::setReg(int regNum, unw_word_t value) { in setReg() function in libunwind::UnwindCursor
1289 setReg(UNW_REG_SP, getReg(UNW_REG_SP) + _info.gp); in step()
Dlibunwind.cpp176 co->setReg(regNum, (pint_t)value); in unw_set_reg()

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