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Searched refs:simm13 (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp277 unsigned simm13 = 0; in DecodeMem() local
279 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeMem()
297 MI.addOperand(MCOperand::CreateImm(simm13)); in DecodeMem()
393 unsigned simm13 = 0; in DecodeJMPL() local
395 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeJMPL()
411 MI.addOperand(MCOperand::CreateImm(simm13)); in DecodeJMPL()
426 unsigned simm13 = 0; in DecodeReturn() local
428 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); in DecodeReturn()
439 MI.addOperand(MCOperand::CreateImm(simm13)); in DecodeReturn()
455 unsigned simm13 = 0; in DecodeSWAP() local
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/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td64 // The ALU instructions want their simm13 operands as i32 immediates.
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
98 // (sllx simm13, n)
102 // (xor (sllx sethi), simm13)
103 // (sllx (xor sethi, simm13))
112 // (or (sllx sethi), (or sethi, simm13))
113 // (xnor (sllx sethi), (or sethi, simm13))
119 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
179 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
196 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
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DSparcInstrInfo.td64 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
256 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
257 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
258 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
268 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
269 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
328 let rd = 0, rs1 = 1, simm13 = 3 in
334 let isBarrier = 1, isTerminator = 1, rd = 0b1000, rs1 = 0, simm13 = 5 in
402 "jmp %o7+$val", [(retflag simm13:$val)]>;
470 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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DSparcInstrAliases.td300 // mov simm13, rd -> or %g0, simm13, rd
301 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
DSparcInstrFormats.td134 bits<13> simm13;
140 let Inst{12-0} = simm13;
/external/valgrind/main/VEX/priv/
Dhost_arm_defs.h137 Int simm13; /* -4095 .. +4095 */ member
148 extern ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 );
Dhost_arm_defs.c219 ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 ) { in ARMAMode1_RI() argument
223 am->ARMam1.RI.simm13 = simm13; in ARMAMode1_RI()
224 vassert(-4095 <= simm13 && simm13 <= 4095); in ARMAMode1_RI()
240 vex_printf("%d(", am->ARMam1.RI.simm13); in ppARMAMode1()
2949 if (am->ARMam1.RI.simm13 < 0) { in do_load_or_store32()
2951 simm12 = -am->ARMam1.RI.simm13; in do_load_or_store32()
2954 simm12 = am->ARMam1.RI.simm13; in do_load_or_store32()
3106 if (am->ARMam1.RI.simm13 < 0) { in emit_ARMInstr()
3108 simm12 = -am->ARMam1.RI.simm13; in emit_ARMInstr()
3111 simm12 = am->ARMam1.RI.simm13; in emit_ARMInstr()
Dhost_arm_isel.c751 && am->ARMam1.RI.simm13 >= -4095 in sane_AMode1()
752 && am->ARMam1.RI.simm13 <= 4095 ); in sane_AMode1()
/external/llvm/docs/
DWritingAnLLVMBackend.rst816 [(set i32:$dst, (OpNode i32:$b, simm13:$c))]>;