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Searched refs:v1i32 (Results 1 – 13 of 13) sorted by relevance

/external/llvm/test/CodeGen/R600/
Dllvm.SI.sample-masked.ll8 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
21 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
34 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
47 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
60 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
72 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
84 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
91 declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone
Dllvm.SI.sample.ll143 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
153 declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h78 v1i32 = 32, // 1 x i32 enumerator
199 SimpleTy == MVT::v1i32); in is32BitVector()
287 case v1i32: in getVectorElementType()
353 case v1i32: in getVectorNumElements()
393 case v1i32: return 32; in getSizeInBits()
535 if (NumElements == 1) return MVT::v1i32; in getVectorVT()
DValueTypes.td55 def v1i32 : ValueType<32 , 32>; // 1 x i32 vector value
/external/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
11 ; FIXME: Currently XTN is generated for v1i32, but it can be optimized.
Darm64-neon-copy.ll873 define <4 x i32> @testDUP.v1i32(<1 x i32> %a) {
874 ; CHECK-LABEL: testDUP.v1i32:
/external/llvm/test/CodeGen/ARM/
Dv1-constant-fold.ll3 ; PR15611. Check that we don't crash when constant folding v1i32 types.
/external/llvm/lib/IR/
DValueTypes.cpp150 case MVT::v1i32: return "v1i32"; in getEVTString()
218 case MVT::v1i32: return VectorType::get(Type::getInt32Ty(Context), 1); in getTypeForEVT()
/external/llvm/lib/Target/R600/
DSIRegisterInfo.td178 def VReg_32 : RegisterClass<"AMDGPU", [i32, f32, v1i32], 32, (add VGPR_32)>;
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp91 case MVT::v1i32: return "MVT::v1i32"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td166 def llvm_v1i32_ty : LLVMType<v1i32>; // 1 x i32
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td5295 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
5302 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5307 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
5495 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5502 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5511 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5526 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5541 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
6775 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
DAArch64ISelLowering.cpp7920 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32 in getPreferredVectorAction()