Searched refs:v1i8 (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 65 v1i8 = 19, // 1 x i8 enumerator
274 case v1i8 : in getVectorElementType()
351 case v1i8: in getVectorNumElements()
379 case v1i8: in getSizeInBits()
518 if (NumElements == 1) return MVT::v1i8; in getVectorVT()
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| D | ValueTypes.td | 42 def v1i8 : ValueType<16, 19>; // 1 x i8 vector value
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| /external/llvm/test/CodeGen/AArch64/ |
| D | trunc-v1i64.ll | 6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
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| D | arm64-neon-copy.ll | 843 define <8 x i8> @testDUP.v1i8(<1 x i8> %a) {
844 ; CHECK-LABEL: testDUP.v1i8:
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 137 case MVT::v1i8: return "v1i8"; in getEVTString()
205 case MVT::v1i8: return VectorType::get(Type::getInt8Ty(Context), 1); in getTypeForEVT()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 78 case MVT::v1i8: return "MVT::v1i8"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 151 def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 5297 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5514 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5529 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5544 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
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| D | AArch64ISelLowering.cpp | 7920 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32 in getPreferredVectorAction()
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