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/external/llvm/test/CodeGen/X86/
Dvec_floor.ll35 %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
38 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
71 %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
74 declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
107 %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
110 declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
143 %t = call <8 x float> @llvm.rint.v8f32(<8 x float> %p)
146 declare <8 x float> @llvm.rint.v8f32(<8 x float> %p)
179 %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
182 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
Dvec_fabs.ll35 %t = call <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
38 declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
/external/llvm/test/CodeGen/PowerPC/
Dvec_rounding.ll107 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
110 %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
126 declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
129 %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
145 declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
148 %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
164 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
167 %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
Dvec_sqrt.ll11 declare <8 x float> @llvm.sqrt.v8f32(<8 x float> %val)
40 %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x)
Dvec_fmuladd.ll8 declare <8 x float> @llvm.fmuladd.v8f32(<8 x float> %val, <8 x float>, <8 x float>)
31 %fmuladd = call <8 x float> @llvm.fmuladd.v8f32 (<8 x float> %x, <8 x float> %x, <8 x float> %x)
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h98 v8f32 = 48, // 8 x f32 enumerator
218 return (SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || in is256BitVector()
303 case v8f32: in getVectorElementType()
333 case v8f32: in getVectorNumElements()
420 case v8f32: in getSizeInBits()
557 if (NumElements == 8) return MVT::v8f32; in getVectorVT()
DValueTypes.td72 def v8f32 : ValueType<256, 48>; // 8 x f32 vector value
/external/llvm/lib/Target/X86/
DX86InstrFMA.td90 loadv8f32, X86Fmadd, v4f32, v8f32>;
92 loadv8f32, X86Fmsub, v4f32, v8f32>;
95 v4f32, v8f32>;
98 v4f32, v8f32>;
117 loadv8f32, X86Fnmadd, v4f32, v8f32>;
119 loadv8f32, X86Fnmsub, v4f32, v8f32>;
362 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
364 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
366 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
368 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
[all …]
DX86TargetTransformInfo.cpp438 {ISD::VECTOR_SHUFFLE, MVT::v8f32, 1}, // vblendps in getShuffleCost()
621 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, in getCastInstrCost()
622 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, in getCastInstrCost()
623 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, in getCastInstrCost()
624 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, in getCastInstrCost()
634 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, in getCastInstrCost()
635 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, in getCastInstrCost()
636 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, in getCastInstrCost()
637 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, in getCastInstrCost()
654 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, in getCastInstrCost()
[all …]
DX86CallingConv.td49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
105 CCIfType<[v8f32, v4f64, v8i32, v4i64],
249 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
271 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
295 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
419 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
427 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
557 CCIfType<[v8f32, v4f64, v8i32, v4i64],
DX86InstrSSE.td333 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
334 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
356 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
412 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
417 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
418 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
419 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
420 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
421 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
[all …]
DX86InstrAVX512.td51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
[all …]
DX86InstrFragmentsSIMD.td307 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
377 (v8f32 (alignedload256 node:$ptr))>;
425 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
483 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
DX86RegisterInfo.td438 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
463 def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp254 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
255 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
256 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
257 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
283 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
284 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
/external/llvm/test/CodeGen/R600/
Dftrunc.ll8 declare <8 x float> @llvm.trunc.v8f32(<8 x float>) nounwind readnone
77 %y = call <8 x float> @llvm.trunc.v8f32(<8 x float> %x) nounwind readnone
Dfceil.ll8 declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone
85 %y = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x) nounwind readnone
/external/llvm/test/CodeGen/AArch64/
Darm64-fmuladd.ll44 …%tmp4 = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> %tmp1, <8 x float> %tmp2, <8 x float> %tm…
85 declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp346 DecodeSHUFPMask(MVT::v8f32, in EmitAnyX86InstComments()
385 DecodeUNPCKLMask(MVT::v8f32, ShuffleMask); in EmitAnyX86InstComments()
421 DecodeUNPCKHMask(MVT::v8f32, ShuffleMask); in EmitAnyX86InstComments()
440 DecodePSHUFMask(MVT::v8f32, in EmitAnyX86InstComments()
/external/llvm/lib/Target/R600/
DSIRegisterInfo.td173 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
188 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
DAMDGPUISelLowering.cpp148 setOperationAction(ISD::STORE, MVT::v8f32, Promote); in AMDGPUTargetLowering()
149 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
194 setOperationAction(ISD::LOAD, MVT::v8f32, Promote); in AMDGPUTargetLowering()
195 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
DSIInstructions.td2086 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2089 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2130 def : BitConvert <v8f32, v8i32, SReg_256>;
2131 def : BitConvert <v8i32, v8f32, SReg_256>;
2135 def : BitConvert <v8i32, v8f32, VReg_256>;
2136 def : BitConvert <v8f32, v8i32, VReg_256>;
2673 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
/external/llvm/lib/IR/
DValueTypes.cpp166 case MVT::v8f32: return "v8f32"; in getEVTString()
234 case MVT::v8f32: return VectorType::get(Type::getFloatTy(Context), 8); in getTypeForEVT()
/external/llvm/test/CodeGen/ARM/
DfusedMAC.ll215 …%call = tail call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c) noun…
224 declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp107 case MVT::v8f32: return "MVT::v8f32"; in getEnumName()

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