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/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/armv6/
Dcopymem16x16_v6.asm25 pld [r0, #31] ; preload for next 16x16 block
27 ands r4, r0, #15
30 ands r4, r0, #7
33 ands r4, r0, #3
37 ldrb r4, [r0]
38 ldrb r5, [r0, #1]
39 ldrb r6, [r0, #2]
40 ldrb r7, [r0, #3]
50 ldrb r4, [r0, #4]
51 ldrb r5, [r0, #5]
[all …]
Dcopymem8x4_v6.asm25 pld [r0]
26 pld [r0, r1]
27 pld [r0, r1, lsl #1]
29 ands r4, r0, #7
32 ands r4, r0, #3
36 ldrb r4, [r0]
37 ldrb r5, [r0, #1]
45 ldrb r4, [r0, #2]
46 ldrb r5, [r0, #3]
53 ldrb r4, [r0, #4]
[all …]
Dcopymem8x8_v6.asm25 pld [r0]
26 pld [r0, r1]
27 pld [r0, r1, lsl #1]
29 ands r4, r0, #7
32 ands r4, r0, #3
36 ldrb r4, [r0]
37 ldrb r5, [r0, #1]
45 ldrb r4, [r0, #2]
46 ldrb r5, [r0, #3]
53 ldrb r4, [r0, #4]
[all …]
Dsixtappredict8x4_v6.asm16 ; r0 unsigned char *src_ptr,
36 sub r0, r0, r1, lsl #1
39 pld [r0, r3]
42 add r0, r0, #3 ;adjust src only for loading convinience
53 ldrb r6, [r0, #-5] ; load source data
54 ldrb r7, [r0, #-4]
55 ldrb r8, [r0, #-3]
56 ldrb r9, [r0, #-2]
57 ldrb r10, [r0, #-1]
71 ldrb r6, [r0], #1
[all …]
Dfilter_v6.asm22 ; r0 unsigned char *src_ptr
54 ldrb r8, [r0, #-2] ; load source data
55 ldrb r9, [r0, #-1]
56 ldrb r10, [r0], #2
60 ldrb r11, [r0, #-1]
65 ldrb r9, [r0]
73 ldrb r10, [r0, #1]
75 ldrb r11, [r0, #2]
88 ldrneb r8, [r0, #-2] ; load data for next loop
91 ldrneb r9, [r0, #-1]
[all …]
Dbilinearfilter_v6.asm18 ; r0 unsigned char *src_ptr,
35 pld [r0, r7]
50 ldrb r6, [r0] ; load source data
51 ldrb r7, [r0, #1]
52 ldrb r8, [r0, #2]
56 ldrb r9, [r0, #3]
57 ldrb r10, [r0, #4]
70 add r0, r0, #4
88 ldrneb r6, [r0] ; load source data
91 ldrneb r7, [r0, #1]
[all …]
Ddequant_idct_v6.asm15 ; r0 = q
23 ldr r4, [r0] ;input
35 ldr r4, [r0, #4] ;input
38 strh r6, [r0], #2
39 strh r7, [r0], #2
46 ldrne r4, [r0, #4]
49 strh r6, [r0], #2
50 strh r7, [r0], #2
54 sub r0, r0, #32
55 mov r1, r0
[all …]
Ddc_only_idct_add_v6.asm17 ; r0 input_dc
26 add r0, r0, #4 ; input_dc += 4
29 and r0, r12, r0, asr #3 ; input_dc >> 3 + mask
31 orr r0, r0, r0, lsl #16 ; a1 | a1
35 uxtab16 r5, r0, r4 ; a1+2 | a1+0
36 uxtab16 r4, r0, r4, ror #8 ; a1+3 | a1+1
37 uxtab16 r7, r0, r6
38 uxtab16 r6, r0, r6, ror #8
50 uxtab16 r5, r0, r4
51 uxtab16 r4, r0, r4, ror #8
[all …]
Didct_v6.asm19 ; r0 short* input
38 ldr r6, [r0, #(4*2)] ; i5 | i4
39 ldr r12, [r0, #(12*2)] ; i13|i12
40 ldr r14, [r0, #(8*2)] ; i9 | i8
59 ldr r11, [r0] ; i1 | i0
74 str r6, [r0, #(4*2)] ; o5 | o4
75 str r7, [r0, #(8*2)] ; o9 | o8
76 str r10,[r0, #(12*2)] ; o13|o12
77 str r9, [r0], #4 ; o1 | o0
81 sub r0, r0, #8 ; reset input/output
[all …]
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/ppc/
Drecon_altivec.asm21 vaddshs v2, v2, v3 ;# v2 = r0..r7
26 vpkshus v2, v2, v3 ;# v2 = 8-bit r0..r15
38 mfspr r0, 256 ;# get old VRSAVE
39 stw r0, -8(r1) ;# save old VRSAVE to stack
40 oris r0, r0, 0xf000
41 mtspr 256,r0 ;# set VRSAVE
60 vaddshs v2, v2, v3 ;# v2 = r0..r7
64 vpkshus v2, v2, v3 ;# v3 = 8-bit r0..r15
66 lwz r0, 0(r10)
68 stw r0, 0(\Dst)
[all …]
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/
Dvp9_reconintra_neon.asm32 ; r0 uint8_t *dst
39 vst1.32 {d0[0]}, [r0], r1
40 vst1.32 {d0[0]}, [r0], r1
41 vst1.32 {d0[0]}, [r0], r1
42 vst1.32 {d0[0]}, [r0], r1
49 ; r0 uint8_t *dst
56 vst1.8 {d0}, [r0], r1
57 vst1.8 {d0}, [r0], r1
58 vst1.8 {d0}, [r0], r1
59 vst1.8 {d0}, [r0], r1
[all …]
Dvp9_idct32x32_1_add_neon.asm70 ; r0 int16_t input
78 ldrsh r0, [r0]
85 mul r0, r0, r12 ; input[0] * cospi_16_64
86 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
87 asr r0, r0, #14 ; >> DCT_CONST_BITS
90 mul r0, r0, r12 ; out * cospi_16_64
92 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
93 asr r0, r0, #14 ; >> DCT_CONST_BITS
96 add r0, r0, #32 ; + (1 <<((6) - 1))
97 asrs r0, r0, #6 ; >> 6
[all …]
Dvp9_idct16x16_1_add_neon.asm21 ; r0 int16_t input
26 ldrsh r0, [r0]
33 mul r0, r0, r12 ; input[0] * cospi_16_64
34 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
35 asr r0, r0, #14 ; >> DCT_CONST_BITS
38 mul r0, r0, r12 ; out * cospi_16_64
40 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
41 asr r0, r0, #14 ; >> DCT_CONST_BITS
44 add r0, r0, #32 ; + (1 <<((6) - 1))
45 asr r0, r0, #6 ; >> 6
[all …]
Dvp9_idct4x4_1_add_neon.asm21 ; r0 int16_t input
26 ldrsh r0, [r0]
33 mul r0, r0, r12 ; input[0] * cospi_16_64
34 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
35 asr r0, r0, #14 ; >> DCT_CONST_BITS
38 mul r0, r0, r12 ; out * cospi_16_64
40 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
41 asr r0, r0, #14 ; >> DCT_CONST_BITS
44 add r0, r0, #8 ; + (1 <<((4) - 1))
45 asr r0, r0, #4 ; >> 4
[all …]
Dvp9_dc_only_idct_add_neon.asm21 ; r0 int input_dc
34 mul r0, r0, r12 ; input_dc * cospi_16_64
35 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
36 asr r0, r0, #14 ; >> DCT_CONST_BITS
39 mul r0, r0, r12 ; out * cospi_16_64
40 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
41 asr r0, r0, #14 ; >> DCT_CONST_BITS
44 add r0, r0, #8 ; + (1 <<((4) - 1))
45 asr r0, r0, #4 ; >> 4
47 vdup.16 q0, r0; ; duplicate a1
Dvp9_idct8x8_1_add_neon.asm21 ; r0 int16_t input
26 ldrsh r0, [r0]
33 mul r0, r0, r12 ; input[0] * cospi_16_64
34 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
35 asr r0, r0, #14 ; >> DCT_CONST_BITS
38 mul r0, r0, r12 ; out * cospi_16_64
40 add r0, r0, #0x2000 ; +(1 << ((DCT_CONST_BITS) - 1))
41 asr r0, r0, #14 ; >> DCT_CONST_BITS
44 add r0, r0, #16 ; + (1 <<((5) - 1))
45 asr r0, r0, #5 ; >> 5
[all …]
Dvp9_copy_neon.asm34 pld [r0, r1, lsl #1]
35 vld1.8 {q0-q1}, [r0]!
36 vld1.8 {q2-q3}, [r0], lr
44 pld [r0, r1, lsl #1]
45 vld1.8 {q0-q1}, [r0], r1
46 pld [r0, r1, lsl #1]
47 vld1.8 {q2-q3}, [r0], r1
55 pld [r0, r1, lsl #1]
56 vld1.8 {q0}, [r0], r1
57 pld [r0, r1, lsl #1]
[all …]
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/
Didct_dequant_0_2x_neon.asm19 ; r0 *q
36 ldrh r12, [r0] ; lo q
37 ldrh r4, [r0, #32] ; hi q
39 strh r5, [r0]
40 strh r5, [r0, #32]
43 mul r0, r12, r1
44 add r0, r0, #4
45 asr r0, r0, #3
46 vdup.16 q0, r0
48 mul r0, r4, r1
[all …]
Dbuildintrapredictorsmby_neon.asm20 ; r0 unsigned char *y_buffer
58 sub r6, r0, r2
76 sub r0, r0, #1
79 ldrb r3, [r0], r2
80 ldrb r4, [r0], r2
81 ldrb r5, [r0], r2
82 ldrb r6, [r0], r2
89 ldrb r3, [r0], r2
90 ldrb r4, [r0], r2
91 ldrb r5, [r0], r2
[all …]
Dsad8_neon.asm28 vld1.8 {d0}, [r0], r1
31 vld1.8 {d2}, [r0], r1
36 vld1.8 {d4}, [r0], r1
41 vld1.8 {d6}, [r0], r1
46 vld1.8 {d0}, [r0], r1
51 vld1.8 {d2}, [r0], r1
56 vld1.8 {d4}, [r0], r1
61 vld1.8 {d6}, [r0], r1
71 vmov.32 r0, d0[0]
85 vld1.8 {d0}, [r0], r1
[all …]
Dmbloopfilter_neon.asm24 ; r0 unsigned char *src,
33 sub r0, r0, r1, lsl #1 ; move src pointer down by 4 lines
35 add r12, r0, r1, lsr #1 ; move src pointer up by 1 line
37 vld1.u8 {q3}, [r0@128], r1 ; p3
39 vld1.u8 {q5}, [r0@128], r1 ; p1
41 vld1.u8 {q7}, [r0@128], r1 ; q0
43 vld1.u8 {q9}, [r0@128], r1 ; q2
49 add r0, r12, r1, lsr #1
52 vst1.u8 {q5}, [r0@128],r1 ; store op1
54 vst1.u8 {q7}, [r0@128],r1 ; store oq0
[all …]
Dloopfiltersimpleverticaledge_neon.asm20 ; r0 unsigned char *s, PRESERVE
25 sub r0, r0, #2 ; move src pointer down by 2 columns
27 add r3, r0, r1
29 vld4.8 {d6[0], d7[0], d8[0], d9[0]}, [r0], r12
31 vld4.8 {d6[2], d7[2], d8[2], d9[2]}, [r0], r12
33 vld4.8 {d6[4], d7[4], d8[4], d9[4]}, [r0], r12
35 vld4.8 {d6[6], d7[6], d8[6], d9[6]}, [r0], r12
38 vld4.8 {d10[0], d11[0], d12[0], d13[0]}, [r0], r12
40 vld4.8 {d10[2], d11[2], d12[2], d13[2]}, [r0], r12
42 vld4.8 {d10[4], d11[4], d12[4], d13[4]}, [r0], r12
[all …]
Dsad16_neon.asm21 ; r0 unsigned char *src_ptr
27 vld1.8 {q0}, [r0], r1
30 vld1.8 {q1}, [r0], r1
36 vld1.8 {q2}, [r0], r1
42 vld1.8 {q3}, [r0], r1
49 vld1.8 {q0}, [r0], r1
55 vld1.8 {q1}, [r0], r1
61 vld1.8 {q2}, [r0], r1
67 vld1.8 {q3}, [r0], r1
74 vld1.8 {q0}, [r0], r1
[all …]
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/arm/armv6/
Dvp8_fast_quantize_b_armv6.asm22 ; r0 BLOCK *b
27 ldr r3, [r0, #vp8_block_coeff] ; coeff
28 ldr r4, [r0, #vp8_block_quant_fast] ; quant_fast
29 ldr r5, [r0, #vp8_block_round] ; round
44 ldr r10, [r5], #4 ; [r1 | r0]
50 sadd16 r9, r9, r10 ; [x1+r1 | x0+r0]
54 smulbb r0, r9, r11 ; [(x0+r0)*q0]
61 pkhtb r0, r9, r0, asr #16 ; [y1 | y0]
67 eor r0, r0, lr ; [(y1 ^ sz1) | (y0 ^ sz0)]
72 ssub16 r0, r0, lr ; x = (y ^ sz) - sz
[all …]
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/arm/armv5te/
Dboolhuff_armv5te.asm27 ; needs vp8_writer in r0
31 push {r0-r3, r12, lr} ; rest of regs are preserved by subroutine call
32 ldr r2, [r0, #vp8_writer_buffer_end]
33 ldr r3, [r0, #vp8_writer_error]
35 mov r0, $start
37 pop {r0-r3, r12, lr}
40 ; r0 BOOL_CODER *br
44 str r2, [r0, #vp8_writer_buffer_end]
48 str r12, [r0, #vp8_writer_lowvalue]
49 str r3, [r0, #vp8_writer_range]
[all …]

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