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Searched refs:MRMSrcReg (Results 1 – 20 of 20) sorted by relevance

/external/llvm/lib/Target/X86/
DX86InstrExtension.td43 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
51 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
59 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
69 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
77 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
85 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
98 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
113 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
121 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
129 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
[all …]
DX86InstrMMX.td93 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
111 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
133 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
150 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
167 def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
181 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
192 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
214 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
239 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
254 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
[all …]
DX86InstrXOP.td15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
42 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
57 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
70 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
82 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
114 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
132 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
162 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
188 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
216 def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
[all …]
DX86Instr3DNow.td37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
57 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
DX86InstrFMA.td25 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
41 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
135 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
223 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
243 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
254 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
279 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
299 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
320 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
324 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
DX86InstrAVX512.td104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
[all …]
DX86InstrSSE.td236 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
258 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
283 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
305 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
541 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
847 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1390 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1397 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1406 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1412 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
[all …]
DX86InstrSystem.td132 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
135 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
151 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
154 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
189 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
191 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
193 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
213 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
221 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
227 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
[all …]
DX86InstrCMovSetCC.td21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
DX86InstrVMX.td56 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
60 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
DX86InstrArithmetic.td157 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
162 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
167 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
207 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
213 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
219 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
225 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
231 def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32
237 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
752 : ITy<opcode, MRMSrcReg, typeinfo,
[all …]
DX86InstrInfo.td1064 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1072 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1080 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1089 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1097 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1105 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1334 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1336 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1338 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1340 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
[all …]
DX86CodeEmitter.cpp190 case X86II::MRMSrcReg: { in determineREX()
920 case X86II::MRMSrcReg: in emitVEXOpcodePrefix()
1262 case X86II::MRMSrcReg: { in emitInstruction()
DX86InstrShiftRotate.td863 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
876 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
DX86InstrFormats.td23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h251 MRMSrcReg = 5, enumerator
656 case X86II::MRMSrcReg: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp848 case X86II::MRMSrcReg: in EmitVEXOpcodePrefix()
1039 case X86II::MRMSrcReg: in DetermineREXPrefix()
1373 case X86II::MRMSrcReg: in EncodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp86 MRMSrcReg = 5, enumerator
132 form == X86Local::MRMSrcReg || in isRegFormat()
607 case X86Local::MRMSrcReg: in emitInstructionSpecifier()
819 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem: in emitDecodePath()
/external/llvm/test/TableGen/
DTargetInstrInfo.td50 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
/external/llvm/docs/
DWritingAnLLVMBackend.rst1814 case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte