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Searched refs:SXTW (Results 1 – 24 of 24) sorted by relevance

/external/chromium_org/v8/src/arm64/
Dregexp-macro-assembler-arm64.cc219 __ Add(x10, input_end(), Operand(current_input_offset(), SXTW)); in CheckAtStart()
230 __ Add(x10, input_end(), Operand(current_input_offset(), SXTW)); in CheckNotAtStart()
256 Operand(current_input_offset(), SXTW)); in CheckCharacters()
320 Operand(capture_start_offset, SXTW)); in CheckNotBackReferenceIgnoreCase()
323 Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
326 Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
361 __ Cmp(current_input_offset().X(), Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
383 __ Add(x0, input_end(), Operand(capture_start_offset, SXTW)); in CheckNotBackReferenceIgnoreCase()
387 __ Add(x1, input_end(), Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
436 __ Add(capture_start_address, input_end(), Operand(w10, SXTW)); in CheckNotBackReference()
[all …]
Dcodegen-arm64.cc488 __ Ldrh(result, MemOperand(string, index, SXTW, 1)); in Generate()
492 __ Ldrb(result, MemOperand(string, index, SXTW)); in Generate()
Dlithium-codegen-arm64.cc1524 : Operand(ToRegister32(instr->right()), SXTW); in DoAddE()
1696 __ Ldr(scratch, MemOperand(elements, length, SXTW, kPointerSizeLog2)); in DoApplyArguments()
3039 __ Add(result, base, Operand(ToRegister32(instr->offset()), SXTW)); in DoInnerAllocatedObject()
3433 return MemOperand(base, key, SXTW, element_size_shift); in PrepareKeyedExternalArrayOperand()
3438 return MemOperand(scratch, key, SXTW, element_size_shift); in PrepareKeyedExternalArrayOperand()
3563 __ Add(base, elements, Operand(key, SXTW, element_size_shift)); in PrepareKeyedArrayOperand()
3567 return MemOperand(base, key, SXTW, element_size_shift); in PrepareKeyedArrayOperand()
3904 __ Cmp(result, Operand(result, SXTW)); in DoMathFloorI()
4179 __ Cmp(result, Operand(result.W(), SXTW)); in DoMathRoundI()
4466 __ Cmp(result.X(), Operand(result, SXTW)); in DoMulI()
[all …]
Dassembler-arm64-inl.h471 ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
524 ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
Dsimulator-arm64.cc927 case SXTW: in ExtendValue()
1453 ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
1512 set_xreg(srcdst, ExtendValue<int64_t>(MemoryRead32(address), SXTW)); in LoadStoreHelper()
1612 set_xreg(rt, ExtendValue<int64_t>(MemoryRead32(address), SXTW)); in LoadStorePairHelper()
1614 MemoryRead32(address + kWRegSize), SXTW)); in LoadStorePairHelper()
Dconstants-arm64.h346 SXTW = 6, enumerator
Ddisasm-arm64.cc1656 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
Dassembler-arm64.cc2157 case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h47 SXTW, enumerator
66 case AArch64_AM::SXTW: return "sxtw"; in getShiftExtendName()
133 case 6: return AArch64_AM::SXTW; in getExtendType()
160 case AArch64_AM::SXTW: return 6; break; in getExtendEncoding()
/external/chromium_org/v8/test/cctest/
Dtest-disasm-arm64.cc144 COMPARE(Mov(x16, Operand(x20, SXTW, 3)), "sbfiz x16, x20, #3, #32"); in TEST_()
384 COMPARE(add(x24, x25, Operand(x26, SXTW, 1)), "add x24, x25, w26, sxtw #1"); in TEST_()
410 COMPARE(sub(x24, x25, Operand(x26, SXTW, 1)), "sub x24, x25, w26, sxtw #1"); in TEST_()
899 COMPARE(ldr(w12, MemOperand(x13, w14, SXTW)), "ldr w12, [x13, w14, sxtw]"); in TEST_()
900 COMPARE(ldr(w15, MemOperand(x16, w17, SXTW, 2)), in TEST_()
909 COMPARE(ldr(x12, MemOperand(x13, w14, SXTW)), "ldr x12, [x13, w14, sxtw]"); in TEST_()
910 COMPARE(ldr(x15, MemOperand(x16, w17, SXTW, 3)), in TEST_()
920 COMPARE(str(w12, MemOperand(x13, w14, SXTW)), "str w12, [x13, w14, sxtw]"); in TEST_()
921 COMPARE(str(w15, MemOperand(x16, w17, SXTW, 2)), in TEST_()
930 COMPARE(str(x12, MemOperand(x13, w14, SXTW)), "str x12, [x13, w14, sxtw]"); in TEST_()
[all …]
Dtest-assembler-arm64.cc310 __ Mvn(x15, Operand(w2, SXTW, 4)); in TEST()
562 __ Orr(x12, x0, Operand(x1, SXTW, 2)); in TEST()
654 __ Orn(x12, x0, Operand(x1, SXTW, 2)); in TEST()
723 __ And(x12, x0, Operand(x1, SXTW, 2)); in TEST()
864 __ Bic(x12, x0, Operand(x1, SXTW, 2)); in TEST()
992 __ Eor(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1061 __ Eon(x12, x0, Operand(x1, SXTW, 2)); in TEST()
2679 __ Ldr(w3, MemOperand(x18, x27, SXTW)); in TEST()
2680 __ Ldr(w4, MemOperand(x18, x28, SXTW, 2)); in TEST()
2683 __ Str(w2, MemOperand(x20, x29, SXTW, 2)); in TEST()
[all …]
/external/vixl/test/
Dtest-disasm-a64.cc120 COMPARE(Mov(x16, Operand(x17, SXTW, 3)), "sbfiz x16, x17, #3, #32"); in TEST()
346 COMPARE(add(x24, x25, Operand(x26, SXTW, 1)), "add x24, x25, w26, sxtw #1"); in TEST()
372 COMPARE(sub(x24, x25, Operand(x26, SXTW, 1)), "sub x24, x25, w26, sxtw #1"); in TEST()
867 COMPARE(ldr(w12, MemOperand(x13, w14, SXTW)), "ldr w12, [x13, w14, sxtw]"); in TEST()
868 COMPARE(ldr(w15, MemOperand(x16, w17, SXTW, 2)), in TEST()
877 COMPARE(ldr(x12, MemOperand(x13, w14, SXTW)), "ldr x12, [x13, w14, sxtw]"); in TEST()
878 COMPARE(ldr(x15, MemOperand(x16, w17, SXTW, 3)), in TEST()
888 COMPARE(str(w12, MemOperand(x13, w14, SXTW)), "str w12, [x13, w14, sxtw]"); in TEST()
889 COMPARE(str(w15, MemOperand(x16, w17, SXTW, 2)), in TEST()
898 COMPARE(str(x12, MemOperand(x13, w14, SXTW)), "str x12, [x13, w14, sxtw]"); in TEST()
[all …]
Dtest-assembler-a64.cc275 __ Mvn(x15, Operand(w2, SXTW, 4)); in TEST()
527 __ Orr(x12, x0, Operand(x1, SXTW, 2)); in TEST()
616 __ Orn(x12, x0, Operand(x1, SXTW, 2)); in TEST()
683 __ And(x12, x0, Operand(x1, SXTW, 2)); in TEST()
821 __ Bic(x12, x0, Operand(x1, SXTW, 2)); in TEST()
945 __ Eor(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1012 __ Eon(x12, x0, Operand(x1, SXTW, 2)); in TEST()
2225 __ Ldr(w3, MemOperand(x18, x27, SXTW)); in TEST()
2226 __ Ldr(w4, MemOperand(x18, x28, SXTW, 2)); in TEST()
2229 __ Str(w2, MemOperand(x20, x29, SXTW, 2)); in TEST()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp138 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) { in runOnMachineFunction()
DHexagonInstrInfo.td1641 def SXTW : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
2217 // Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = SXTW(Rss.lo).
2219 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2221 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2223 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2226 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2228 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2345 (i64 (SXTW (i32 IntRegs:$src1)))>;
2468 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
2473 (i64 (SXTW (LDrib ADDRriS11_0:$src1)))>;
[all …]
DHexagonISelDAGToDAG.cpp456 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, MVT::i64, in SelectIndexedLoadSignExtend64()
477 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, in SelectIndexedLoadSignExtend64()
DHexagonInstrInfoV4.td3216 (i64 (SXTW (LDrib_abs_V4 tglobaladdr:$addr)))>;
3225 (i64 (SXTW (LDrib_abs_V4 FoldGlobalAddr:$addr)))>;
3240 (i64 (SXTW (LDrih_abs_V4 tglobaladdr:$addr)))>,
3252 (i64 (SXTW (LDrih_abs_V4 FoldGlobalAddr:$addr)))>,
3268 (i64 (SXTW (LDriw_abs_V4 tglobaladdr:$addr)))>,
3280 (i64 (SXTW (LDriw_abs_V4 FoldGlobalAddr:$addr)))>,
/external/vixl/src/a64/
Dsimulator-a64.cc350 case SXTW: in ExtendValue()
764 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
807 set_xreg(srcdst, ExtendValue(kXRegSize, MemoryRead32(address), SXTW)); in LoadStoreHelper()
874 set_xreg(rt, ExtendValue(kXRegSize, MemoryRead32(address), SXTW)); in LoadStorePairHelper()
876 MemoryRead32(address + kWRegSizeInBytes), SXTW)); in LoadStorePairHelper()
Dassembler-a64.cc285 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
336 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
1790 case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
Dconstants-a64.h238 SXTW = 6, enumerator
Ddisasm-a64.cc1650 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp953 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
988 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1539 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtendOperands()
1551 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtend8Operands()
2291 .Case("sxtw", AArch64_AM::SXTW) in tryParseOptionalShiftExtend()
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h465 SXTW, enumerator
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp356 return AArch64_AM::SXTW; in getExtendTypeForNode()
691 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32); in SelectExtendedSHL()
761 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32); in SelectAddrModeWRO()
772 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, MVT::i32); in SelectAddrModeWRO()