| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 743 ZEXTLOAD, enumerator
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| D | SelectionDAGNodes.h | 2036 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 148 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in SITargetLowering()
149 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom); in SITargetLowering()
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom); in SITargetLowering()
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand); in SITargetLowering()
298 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr, in LowerParameter()
1070 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT, in performUCharToFloatCombine()
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| D | AMDGPUISelLowering.cpp | 219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand); in AMDGPUTargetLowering()
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand); in AMDGPUTargetLowering()
225 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand); in AMDGPUTargetLowering()
228 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand); in AMDGPUTargetLowering()
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| D | AMDGPUInstructions.td | 152 return L->getExtensionType() == ISD::ZEXTLOAD ||
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| D | R600ISelLowering.cpp | 124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom); in R600TargetLowering()
125 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom); in R600TargetLowering()
1527 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 834 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD in PromoteOperand()
1056 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD in PromoteLoad()
2715 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, in visitAND()
2728 case ISD::ZEXTLOAD: in visitAND()
2737 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, in visitAND()
2842 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { in visitAND()
2843 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, in visitAND()
2862 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { in visitAND()
2863 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, in visitAND()
2890 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { in visitAND()
[all …]
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| D | LegalizeDAG.cpp | 534 HiExtType = ISD::ZEXTLOAD; in ExpandUnalignedLoad()
539 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), in ExpandUnalignedLoad()
555 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, in ExpandUnalignedLoad()
963 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
977 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
1002 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), in LegalizeLoadOps()
1040 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, in LegalizeLoadOps()
1108 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; in LegalizeLoadOps()
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| D | SelectionDAGDumper.cpp | 463 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
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| D | LegalizeVectorOps.cpp | 543 case ISD::ZEXTLOAD: in ExpandLoad()
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| D | LegalizeIntegerTypes.cpp | 1884 } else if (ExtType == ISD::ZEXTLOAD) { in ExpandIntRes_LOAD()
1933 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, in ExpandIntRes_LOAD()
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| D | TargetLowering.cpp | 1303 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { in SimplifySetCC()
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| D | SelectionDAG.cpp | 242 case ISD::ZEXTLOAD: in getExtForLoadExtType()
2542 case ISD::ZEXTLOAD: // '16' bits known in ComputeNumSignBits()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 131 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in XCoreTargetLowering()
135 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); in XCoreTargetLowering()
462 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 222 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in SystemZTargetLowering()
1176 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) { in adjustSubwordCmp()
1187 ISD::ZEXTLOAD); in adjustSubwordCmp()
1216 case ISD::ZEXTLOAD: in isNaturalMemoryOperand()
1369 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) || in adjustICmpTruncate()
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| D | SystemZOperators.td | 225 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 591 bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD); in SelectIndexedLoad()
621 LD->getExtensionType() == ISD::ZEXTLOAD) { in SelectIndexedLoad()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 209 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in NVPTXTargetLowering()
1746 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
1879 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 226 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
379 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); in MipsTargetLowering()
2071 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); in lowerLOAD()
3629 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
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| D | MipsSEISelLowering.cpp | 56 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand); in MipsSETargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 85 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 636 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
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| /external/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 2867 LType = ISD::ZEXTLOAD; in MoveExtToFormExtLoad()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in PPCTargetLowering()
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand); in PPCTargetLowering()
1795 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
1818 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 459 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); in AArch64TargetLowering()
1778 ExtType = ISD::ZEXTLOAD; in LowerFormalArguments()
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