Searched refs:addr_write (Results 1 – 6 of 6) sorted by relevance
30 .addr_write = -1,77 addr == (tlb_entry->addr_write & in tlb_flush_entry()135 return (tlbe->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM; in tlb_is_dirty_ram()144 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; in tlb_reset_dirty_range()146 tlb_entry->addr_write &= TARGET_PAGE_MASK; in tlb_reset_dirty_range()147 tlb_entry->addr_write |= TLB_NOTDIRTY; in tlb_reset_dirty_range()154 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) { in tlb_set_dirty1()155 tlb_entry->addr_write = vaddr; in tlb_set_dirty1()288 te->addr_write = address | TLB_MMIO; in tlb_set_page()291 te->addr_write = address | TLB_NOTDIRTY; in tlb_set_page()[all …]
601 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { in tlb_update_dirty()602 p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) in tlb_update_dirty()606 tlb_entry->addr_write |= TLB_NOTDIRTY; in tlb_update_dirty()
363 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; in helper_le_st_name()378 tlb_addr = env->tlb_table[mmu_idx][index].addr_write; in helper_le_st_name()439 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; in helper_be_st_name()454 tlb_addr = env->tlb_table[mmu_idx][index].addr_write; in helper_be_st_name()
94 target_ulong addr_write; member
142 if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write != in glue()
1569 label_ptr, offsetof(CPUTLBEntry, addr_write)); in tcg_out_qemu_st()