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Searched refs:shld (Results 1 – 25 of 43) sorted by relevance

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/external/llvm/test/CodeGen/X86/
D2006-01-19-ISelFoldingBug.ll2 ; RUN: grep shld | count 1
4 ; Check that the isel does not fold the shld, which already folds a load
Dx86-64-double-shifts-Oz-Os-O2.ll4 ; Verify that we generate shld insruction when we are optimizing for size,
26 ; Verify that we generate shld insruction when we are optimizing for size,
47 ; Verify that we do not generate shld insruction when we are not optimizing
Dx86-64-double-shifts-var.ll20 ; double precision shift instructions we do not generate 'shld' or 'shrd'
30 ; CHECK-NOT: shld
Dshift-coalesce.ll2 ; RUN: grep "shld.*cl"
Dx86-64-double-precision-shift-left.ll4 ; of instructions with lower latencies instead of shld instruction.
Drot64.ll4 ; RUN: grep shld %t | count 2
/external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/
Dgenopcode.asm95 shld ax, bx, 5 label
97 shld ecx, edx, 10 label
98 shld eax, ebx, cl label
/external/llvm/test/MC/X86/
Dintel-syntax.s377 shld DX, BX define
378 shld DX, BX, CL define
379 shld DX, BX, 1 define
380 shld [RAX], BX label
381 shld [RAX], BX, CL label
Dx86-64.s357 shld %bx, %dx label
358 shld %cl, %bx, %dx label
359 shld $1, %bx, %dx label
360 shld %bx, (%rax) label
361 shld %cl, %bx, (%rax) label
/external/linux-tools-perf/perf-3.12.0/arch/sh/lib/
Dmemset-sh4.S62 shld r0,r2 ! number of loops
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td693 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
705 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
715 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
731 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
745 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
759 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
776 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
785 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
794 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
805 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
DX86.td80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
DX86InstrInfo.td2794 // shld/shrd op,op -> shld op, op, CL
2795 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2796 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2797 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2802 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2803 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2804 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
/external/flac/libFLAC/ia32/
Dbitreader_asm.nasm407 shld edi, edx, cl
422 shld edi, edx, cl
485 shld edi, eax, cl
505 shld edi, eax, cl
529 shld edi, eax, cl ; uval <<= parameter <<< 'parameter' bits of tail word
/external/chromium_org/v8/test/cctest/
Dtest-disasm-x87.cc122 __ shld(edx, ecx); in TEST() local
201 __ shld(edx, Operand(ebx, ecx, times_4, 10000)); in TEST() local
Dtest-disasm-ia32.cc122 __ shld(edx, ecx); in TEST() local
201 __ shld(edx, Operand(ebx, ecx, times_4, 10000)); in TEST() local
Dtest-disasm-x64.cc118 __ shld(rdx, rcx); in TEST() local
192 __ shld(rdx, rbx); in TEST() local
/external/chromium_org/v8/src/x87/
Dassembler-x87.h713 void shld(Register dst, Register src) { shld(dst, Operand(src)); } in shld() function
714 void shld(Register dst, const Operand& src);
/external/chromium_org/v8/src/ia32/
Dassembler-ia32.h730 void shld(Register dst, Register src) { shld(dst, Operand(src)); } in shld() function
731 void shld(Register dst, const Operand& src);
/external/mesa3d/src/mesa/x86/
Dassyntax.h648 #define SHLD_L(a,b,c) CHOICE(shldl ARG3(a,b,c), shldl ARG3(a,b,c), _LTOG shld ARG3(c,b,a))
649 #define SHLD2_L(a,b) CHOICE(shldl ARG2(a,b), shldl ARG3(CL,a,b), _LTOG shld ARG3(b,a,CL))
650 #define SHLD_W(a,b,c) CHOICE(shldw ARG3(a,b,c), shldw ARG3(a,b,c), _WTOG shld ARG3(c,b,a))
651 #define SHLD2_W(a,b) CHOICE(shldw ARG2(a,b), shldw ARG3(CL,a,b), _WTOG shld ARG3(b,a,CL))
1369 #define SHLD_L(a,b,c) shld
1370 #define SHLD2_L(a,b) shld L_(b), L_(a)
1371 #define SHLD_W(a,b,c) shld
1372 #define SHLD2_W(a,b) shld W_(b), W_(a)
/external/chromium_org/third_party/mesa/src/src/mesa/x86/
Dassyntax.h648 #define SHLD_L(a,b,c) CHOICE(shldl ARG3(a,b,c), shldl ARG3(a,b,c), _LTOG shld ARG3(c,b,a))
649 #define SHLD2_L(a,b) CHOICE(shldl ARG2(a,b), shldl ARG3(CL,a,b), _LTOG shld ARG3(b,a,CL))
650 #define SHLD_W(a,b,c) CHOICE(shldw ARG3(a,b,c), shldw ARG3(a,b,c), _WTOG shld ARG3(c,b,a))
651 #define SHLD2_W(a,b) CHOICE(shldw ARG2(a,b), shldw ARG3(CL,a,b), _WTOG shld ARG3(b,a,CL))
1369 #define SHLD_L(a,b,c) shld
1370 #define SHLD2_L(a,b) shld L_(b), L_(a)
1371 #define SHLD_W(a,b,c) shld
1372 #define SHLD2_W(a,b) shld W_(b), W_(a)
/external/valgrind/main/docs/internals/
D3_1_BUGSTATUS.txt68 vx1615 fixed 126583 amd64->IR: 0x48 0xF 0xA4 0xC2 (shld $1,%rax,%rdx)
/external/chromium_org/third_party/libyuv/source/
Dscale_win.cc1291 shld edx, eax, 16 // 32.16 in FixedDiv_X86()
1305 shld edx, eax, 16 // 32.16 in FixedDiv1_X86()
/external/qemu/distrib/sdl-1.2.15/src/stdlib/
DSDL_stdlib.c580 shld edx,eax,cl in _allshl()
/external/openssl/crypto/aes/asm/
Daesni-sha1-x86_64.pl645 my $_rol=sub { &shld(@_[0],@_) };

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