404                                       RegLocation rl_src, RegLocation rl_dest, int lit) {  in SmallLiteralDivRem()  argument
405   if ((lit < 0) || (lit >= static_cast<int>(arraysize(magic_table)))) {  in SmallLiteralDivRem()
408   DividePattern pattern = magic_table[lit].pattern;  in SmallLiteralDivRem()
418   LoadConstant(r_magic, magic_table[lit].magic32);  in SmallLiteralDivRem()
431                   32 + magic_table[lit].shift);  in SmallLiteralDivRem()
437       OpRegRegImm(kOpAsr, r_long_mul, r_long_mul, magic_table[lit].shift);  in SmallLiteralDivRem()
448                                         RegLocation rl_src, RegLocation rl_dest, int64_t lit) {  in SmallLiteralDivRem64()  argument
449   if ((lit < 0) || (lit >= static_cast<int>(arraysize(magic_table)))) {  in SmallLiteralDivRem64()
452   DividePattern pattern = magic_table[lit].pattern;  in SmallLiteralDivRem64()
466   if (magic_table[lit].magic64_base >= 0) {  in SmallLiteralDivRem64()
470       uint64_t base = DecodeLogicalImmediate(/*is_wide*/true, magic_table[lit].magic64_base);  in SmallLiteralDivRem64()
471       if (magic_table[lit].magic64_eor >= 0) {  in SmallLiteralDivRem64()
472         uint64_t eor = DecodeLogicalImmediate(/*is_wide*/true, magic_table[lit].magic64_eor);  in SmallLiteralDivRem64()
480     NewLIR3(WIDE(kA64Orr3Rrl), r_magic.GetReg(), rxzr, magic_table[lit].magic64_base);  in SmallLiteralDivRem64()
481     if (magic_table[lit].magic64_eor >= 0) {  in SmallLiteralDivRem64()
483               magic_table[lit].magic64_eor);  in SmallLiteralDivRem64()
488     LoadConstantWide(r_magic, magic_table[lit].magic64);  in SmallLiteralDivRem64()
497       OpRegRegImm(kOpAsr, r_long_mul, r_long_mul, magic_table[lit].shift);  in SmallLiteralDivRem64()
502       OpRegRegImm(kOpAsr, r_long_mul, r_long_mul, magic_table[lit].shift);  in SmallLiteralDivRem64()
515                                     RegLocation rl_src, RegLocation rl_dest, int lit) {  in HandleEasyDivRem()  argument
516   return HandleEasyDivRem64(dalvik_opcode, is_div, rl_src, rl_dest, static_cast<int>(lit));  in HandleEasyDivRem()
522                                       RegLocation rl_src, RegLocation rl_dest, int64_t lit) {  in HandleEasyDivRem64()  argument
526   if (lit < 2) {  in HandleEasyDivRem64()
529   if (!IsPowerOfTwo(lit)) {  in HandleEasyDivRem64()
531       return SmallLiteralDivRem64(dalvik_opcode, is_div, rl_src, rl_dest, lit);  in HandleEasyDivRem64()
533       return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, static_cast<int32_t>(lit));  in HandleEasyDivRem64()
536   int k = LowestSetBit(lit);  in HandleEasyDivRem64()
556     if (lit == 2) {  in HandleEasyDivRem64()
566     if (lit == 2) {  in HandleEasyDivRem64()
568       OpRegRegImm64(kOpAnd, t_reg, t_reg, lit - 1);  in HandleEasyDivRem64()
574       OpRegRegImm64(kOpAnd, t_reg2, t_reg2, lit - 1);  in HandleEasyDivRem64()
587 bool Arm64Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) {  in EasyMultiply()  argument
592 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_d…  in GenDivRemLit()  argument
597 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) {  in GenDivRemLit()  argument
602   LoadConstant(lit_temp, lit);  in GenDivRemLit()
923                                                RegLocation rl_result, int lit,  in GenMultiplyByTwoBitMultiplier()  argument
1007     int64_t lit = mir_graph_->ConstantValueWide(rl_src2);  in GenDivRemLong()  local
1008     if (HandleEasyDivRem64(opcode, is_div, rl_src1, rl_dest, lit)) {  in GenDivRemLong()