Lines Matching refs:SUnit
125 std::vector<SUnit*> PendingQueue;
144 std::vector<SUnit*> LiveRegDefs;
145 std::vector<SUnit*> LiveRegGens;
149 SmallVector<SUnit*, 4> Interferences;
150 typedef DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMapT;
159 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
187 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable()
193 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle()
200 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
208 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
214 bool isReady(SUnit *SU) { in isReady()
219 void ReleasePred(SUnit *SU, const SDep *PredEdge);
220 void ReleasePredecessors(SUnit *SU);
223 void AdvancePastStalls(SUnit *SU);
224 void EmitNode(SUnit *SU);
225 void ScheduleNodeBottomUp(SUnit*);
227 void UnscheduleNodeBottomUp(SUnit*);
229 void BacktrackBottomUp(SUnit*, SUnit*);
230 SUnit *CopyAndMoveSuccessors(SUnit*);
231 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
234 SmallVectorImpl<SUnit*>&);
235 bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
239 SUnit *PickNodeToScheduleBottomUp();
244 SUnit *CreateNewSUnit(SDNode *N) { in CreateNewSUnit()
246 SUnit *NewNode = newSUnit(N); in CreateNewSUnit()
255 SUnit *CreateClone(SUnit *N) { in CreateClone()
257 SUnit *NewNode = Clone(N); in CreateClone()
366 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred()
367 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
526 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { in ReleasePredecessors()
528 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in ReleasePredecessors()
536 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef; in ReleasePredecessors()
559 SUnit *Def = &SUnits[N->getNodeId()]; in ReleasePredecessors()
623 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) { in AdvancePastStalls()
665 void ScheduleDAGRRList::EmitNode(SUnit *SU) { in EmitNode()
702 static void resetVRegCycle(SUnit *SU);
707 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { in ScheduleNodeBottomUp()
741 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in ScheduleNodeBottomUp()
793 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
806 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { in UnscheduleNodeBottomUp()
810 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in UnscheduleNodeBottomUp()
852 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in UnscheduleNodeBottomUp()
892 std::vector<SUnit*>::const_iterator I = (Sequence.end() - LookAhead); in RestoreHazardCheckerBottomUp()
894 for (std::vector<SUnit*>::const_iterator E = Sequence.end(); I != E; ++I) { in RestoreHazardCheckerBottomUp()
895 SUnit *SU = *I; in RestoreHazardCheckerBottomUp()
905 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { in BacktrackBottomUp()
906 SUnit *OldSU = Sequence.back(); in BacktrackBottomUp()
927 static bool isOperandOf(const SUnit *SU, SDNode *N) { in isOperandOf()
938 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { in CopyAndMoveSuccessors()
946 SUnit *NewSU; in CopyAndMoveSuccessors()
988 SUnit *LoadSU; in CopyAndMoveSuccessors()
1000 SUnit *NewSU = CreateNewSUnit(N); in CopyAndMoveSuccessors()
1023 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in CopyAndMoveSuccessors()
1032 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in CopyAndMoveSuccessors()
1060 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
1072 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
1104 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in CopyAndMoveSuccessors()
1111 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in CopyAndMoveSuccessors()
1112 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in CopyAndMoveSuccessors()
1116 SUnit *SuccSU = I->getSUnit(); in CopyAndMoveSuccessors()
1137 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, in InsertCopiesAndMoveSuccs()
1140 SmallVectorImpl<SUnit*> &Copies) { in InsertCopiesAndMoveSuccs()
1141 SUnit *CopyFromSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1145 SUnit *CopyToSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1151 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in InsertCopiesAndMoveSuccs()
1152 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in InsertCopiesAndMoveSuccs()
1156 SUnit *SuccSU = I->getSUnit(); in InsertCopiesAndMoveSuccs()
1207 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, in CheckForLiveRegDef()
1208 std::vector<SUnit*> &LiveRegDefs, in CheckForLiveRegDef()
1229 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked()
1230 std::vector<SUnit*> &LiveRegDefs, in CheckForLiveRegDefMasked()
1257 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) { in DelayForLiveRegsBottomUp()
1266 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in DelayForLiveRegsBottomUp()
1333 SUnit *SU = Interferences[i-1]; in releaseInterferences()
1359 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { in PickNodeToScheduleBottomUp()
1360 SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop(); in PickNodeToScheduleBottomUp()
1389 SUnit *TrySU = Interferences[i]; in PickNodeToScheduleBottomUp()
1394 SUnit *BtSU = nullptr; in PickNodeToScheduleBottomUp()
1437 SUnit *TrySU = Interferences[0]; in PickNodeToScheduleBottomUp()
1441 SUnit *LRDef = LiveRegDefs[Reg]; in PickNodeToScheduleBottomUp()
1454 SUnit *NewDef = nullptr; in PickNodeToScheduleBottomUp()
1462 SmallVector<SUnit*, 2> Copies; in PickNodeToScheduleBottomUp()
1489 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; in ListScheduleBottomUp()
1504 SUnit *SU = PickNodeToScheduleBottomUp(); in ListScheduleBottomUp()
1535 struct queue_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1536 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; } in isReady()
1545 bool operator()(SUnit* left, SUnit* right) const { in operator ()()
1564 bool operator()(SUnit* left, SUnit* right) const;
1578 bool operator()(SUnit* left, SUnit* right) const;
1592 bool isReady(SUnit *SU, unsigned CurCycle) const;
1594 bool operator()(SUnit* left, SUnit* right) const;
1609 bool isReady(SUnit *SU, unsigned CurCycle) const;
1611 bool operator()(SUnit* left, SUnit* right) const;
1616 std::vector<SUnit*> Queue;
1622 std::vector<SUnit> *SUnits;
1672 void initNodes(std::vector<SUnit> &sunits) override;
1674 void addNode(const SUnit *SU) override;
1676 void updateNode(const SUnit *SU) override;
1684 unsigned getNodePriority(const SUnit *SU) const;
1686 unsigned getNodeOrdering(const SUnit *SU) const { in getNodeOrdering()
1694 void push(SUnit *U) override { in push()
1700 void remove(SUnit *SU) override { in remove()
1703 std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(), in remove()
1715 bool HighRegPressure(const SUnit *SU) const;
1717 bool MayReduceRegPressure(SUnit *SU) const;
1719 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1721 void scheduledNode(SUnit *SU) override;
1723 void unscheduledNode(SUnit *SU) override;
1726 bool canClobber(const SUnit *SU, const SUnit *Op);
1733 static SUnit *popFromQueueImpl(std::vector<SUnit*> &Q, SF &Picker) { in popFromQueueImpl()
1734 std::vector<SUnit *>::iterator Best = Q.begin(); in popFromQueueImpl()
1735 for (std::vector<SUnit *>::iterator I = std::next(Q.begin()), in popFromQueueImpl()
1739 SUnit *V = *Best; in popFromQueueImpl()
1747 SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker, ScheduleDAG *DAG) { in popFromQueue()
1775 bool isReady(SUnit *U) const override { in isReady()
1779 SUnit *pop() override { in pop()
1782 SUnit *V = popFromQueue(Queue, Picker, scheduleDAG); in pop()
1790 std::vector<SUnit*> DumpQueue = Queue; in dump()
1793 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); in dump()
1824 static int checkSpecialNodes(const SUnit *left, const SUnit *right) { in checkSpecialNodes()
1835 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber()
1841 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in CalcNodeSethiUllmanNumber()
1844 SUnit *PredSU = I->getSUnit(); in CalcNodeSethiUllmanNumber()
1870 void RegReductionPQBase::addNode(const SUnit *SU) { in addNode()
1877 void RegReductionPQBase::updateNode(const SUnit *SU) { in updateNode()
1884 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { in getNodePriority()
1939 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { in HighRegPressure()
1943 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); in HighRegPressure()
1947 SUnit *PredSU = I->getSUnit(); in HighRegPressure()
1965 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const { in MayReduceRegPressure()
1990 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const { in RegPressureDiff()
1993 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); in RegPressureDiff()
1997 SUnit *PredSU = I->getSUnit(); in RegPressureDiff()
2030 void RegReductionPQBase::scheduledNode(SUnit *SU) { in scheduledNode()
2037 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in scheduledNode()
2041 SUnit *PredSU = I->getSUnit(); in scheduledNode()
2099 void RegReductionPQBase::unscheduledNode(SUnit *SU) { in unscheduledNode()
2119 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in unscheduledNode()
2123 SUnit *PredSU = I->getSUnit(); in unscheduledNode()
2186 static unsigned closestSucc(const SUnit *SU) { in closestSucc()
2188 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in closestSucc()
2205 static unsigned calcMaxScratches(const SUnit *SU) { in calcMaxScratches()
2207 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in calcMaxScratches()
2217 static bool hasOnlyLiveInOpers(const SUnit *SU) { in hasOnlyLiveInOpers()
2219 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in hasOnlyLiveInOpers()
2222 const SUnit *PredSU = I->getSUnit(); in hasOnlyLiveInOpers()
2240 static bool hasOnlyLiveOutUses(const SUnit *SU) { in hasOnlyLiveOutUses()
2242 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in hasOnlyLiveOutUses()
2245 const SUnit *SuccSU = I->getSUnit(); in hasOnlyLiveOutUses()
2269 static void initVRegCycle(SUnit *SU) { in initVRegCycle()
2280 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in initVRegCycle()
2289 static void resetVRegCycle(SUnit *SU) { in resetVRegCycle()
2293 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); in resetVRegCycle()
2296 SUnit *PredSU = I->getSUnit(); in resetVRegCycle()
2307 static bool hasVRegCycleUse(const SUnit *SU) { in hasVRegCycleUse()
2312 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); in hasVRegCycleUse()
2327 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) { in BUHasStall()
2337 static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref, in BUCompareLatency()
2388 static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) { in BURRSort()
2492 bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2500 bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2519 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2534 bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2566 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2576 static bool canEnableCoalescing(SUnit *SU) { in canEnableCoalescing()
2600 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2659 void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) { in initNodes()
2682 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) { in canClobber()
2703 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU, in canClobberReachingPhysRegUse()
2713 for (SUnit::const_succ_iterator SI = SU->Succs.begin(), SE = SU->Succs.end(); in canClobberReachingPhysRegUse()
2715 SUnit *SuccSU = SI->getSUnit(); in canClobberReachingPhysRegUse()
2716 for (SUnit::const_pred_iterator PI = SuccSU->Preds.begin(), in canClobberReachingPhysRegUse()
2740 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, in canClobberPhysRegDefs()
2811 SUnit *SU = &(*SUnits)[i]; in PrescheduleNodesWithMultipleUses()
2829 SUnit *PredSU = nullptr; in PrescheduleNodesWithMultipleUses()
2830 for (SUnit::const_pred_iterator II = SU->Preds.begin(), in PrescheduleNodesWithMultipleUses()
2854 for (SUnit::const_succ_iterator II = PredSU->Succs.begin(), in PrescheduleNodesWithMultipleUses()
2856 SUnit *PredSuccSU = II->getSUnit(); in PrescheduleNodesWithMultipleUses()
2879 SUnit *SuccSU = Edge.getSUnit(); in PrescheduleNodesWithMultipleUses()
2902 SUnit *SU = &(*SUnits)[i]; in AddPseudoTwoAddrDeps()
2921 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; in AddPseudoTwoAddrDeps()
2923 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(), in AddPseudoTwoAddrDeps()
2926 SUnit *SuccSU = I->getSUnit(); in AddPseudoTwoAddrDeps()