Lines Matching refs:Op0
1512 SDValue Op0 = N0; in SimplifySetCC() local
1513 if (Op0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
1514 Op0 = Op0.getOperand(0); in SimplifySetCC()
1516 if ((Op0.getOpcode() == ISD::XOR) && in SimplifySetCC()
1517 Op0.getOperand(0).getOpcode() == ISD::SETCC && in SimplifySetCC()
1518 Op0.getOperand(1).getOpcode() == ISD::SETCC) { in SimplifySetCC()
1521 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), in SimplifySetCC()
1524 if (Op0.getOpcode() == ISD::AND && in SimplifySetCC()
1525 isa<ConstantSDNode>(Op0.getOperand(1)) && in SimplifySetCC()
1526 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { in SimplifySetCC()
1528 if (Op0.getValueType().bitsGT(VT)) in SimplifySetCC()
1529 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
1530 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
1532 else if (Op0.getValueType().bitsLT(VT)) in SimplifySetCC()
1533 Op0 = DAG.getNode(ISD::AND, dl, VT, in SimplifySetCC()
1534 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
1537 return DAG.getSetCC(dl, VT, Op0, in SimplifySetCC()
1538 DAG.getConstant(0, Op0.getValueType()), in SimplifySetCC()
1541 if (Op0.getOpcode() == ISD::AssertZext && in SimplifySetCC()
1542 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) in SimplifySetCC()
1543 return DAG.getSetCC(dl, VT, Op0, in SimplifySetCC()
1544 DAG.getConstant(0, Op0.getValueType()), in SimplifySetCC()