61                             SmallVectorImpl<MachineOperand> &Cond) {  in parseCondBranch()  argument
68     Cond.push_back(LastInst->getOperand(0));  in parseCondBranch()
75     Cond.push_back(MachineOperand::CreateImm(-1));  in parseCondBranch()
76     Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));  in parseCondBranch()
77     Cond.push_back(LastInst->getOperand(0));  in parseCondBranch()
84     Cond.push_back(MachineOperand::CreateImm(-1));  in parseCondBranch()
85     Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));  in parseCondBranch()
86     Cond.push_back(LastInst->getOperand(0));  in parseCondBranch()
87     Cond.push_back(LastInst->getOperand(1));  in parseCondBranch()
95                                    SmallVectorImpl<MachineOperand> &Cond,  in AnalyzeBranch()  argument
122       parseCondBranch(LastInst, TBB, Cond);  in AnalyzeBranch()
156     parseCondBranch(SecondLastInst, TBB, Cond);  in AnalyzeBranch()
185     SmallVectorImpl<MachineOperand> &Cond) const {  in ReverseBranchCondition()
186   if (Cond[0].getImm() != -1) {  in ReverseBranchCondition()
188     AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm();  in ReverseBranchCondition()
189     Cond[0].setImm(AArch64CC::getInvertedCondCode(CC));  in ReverseBranchCondition()
192     switch (Cond[1].getImm()) {  in ReverseBranchCondition()
196       Cond[1].setImm(AArch64::CBNZW);  in ReverseBranchCondition()
199       Cond[1].setImm(AArch64::CBZW);  in ReverseBranchCondition()
202       Cond[1].setImm(AArch64::CBNZX);  in ReverseBranchCondition()
205       Cond[1].setImm(AArch64::CBZX);  in ReverseBranchCondition()
208       Cond[1].setImm(AArch64::TBNZW);  in ReverseBranchCondition()
211       Cond[1].setImm(AArch64::TBZW);  in ReverseBranchCondition()
214       Cond[1].setImm(AArch64::TBNZX);  in ReverseBranchCondition()
217       Cond[1].setImm(AArch64::TBZX);  in ReverseBranchCondition()
257     const SmallVectorImpl<MachineOperand> &Cond) const {  in instantiateCondBranch()
258   if (Cond[0].getImm() != -1) {  in instantiateCondBranch()
260     BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);  in instantiateCondBranch()
264         BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg());  in instantiateCondBranch()
265     if (Cond.size() > 3)  in instantiateCondBranch()
266       MIB.addImm(Cond[3].getImm());  in instantiateCondBranch()
273     const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {  in InsertBranch()  argument
278     if (Cond.empty()) // Unconditional branch?  in InsertBranch()
281       instantiateCondBranch(MBB, DL, TBB, Cond);  in InsertBranch()
286   instantiateCondBranch(MBB, DL, TBB, Cond);  in InsertBranch()
370     const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond,  in canInsertSelect()  argument
381   unsigned ExtraCondLat = Cond.size() != 1;  in canInsertSelect()
413                                     const SmallVectorImpl<MachineOperand> &Cond,  in insertSelect()  argument
419   switch (Cond.size()) {  in insertSelect()
423     CC = AArch64CC::CondCode(Cond[0].getImm());  in insertSelect()
428     switch (Cond[1].getImm()) {  in insertSelect()
448     unsigned SrcReg = Cond[2].getReg();  in insertSelect()
467     switch (Cond[1].getImm()) {  in insertSelect()
480     if (Cond[1].getImm() == AArch64::TBZW || Cond[1].getImm() == AArch64::TBNZW)  in insertSelect()
482           .addReg(Cond[2].getReg())  in insertSelect()
484               AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 32));  in insertSelect()
487           .addReg(Cond[2].getReg())  in insertSelect()
489               AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));  in insertSelect()