Lines Matching refs:b11
364 defm MOVK : InsertImmediate<0b11, "movk">;
600 defm RORV : Shift<0b11, "ror", rotr>;
661 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
666 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
674 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
689 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
690 defm BICS : LogicalRegS<0b11, 1, "bics",
1057 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1060 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1115 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1121 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1122 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1125 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1129 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1136 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1279 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1294 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1297 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1410 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1420 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1440 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1459 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1464 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1479 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1482 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1617 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1627 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1658 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1664 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1671 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1675 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1684 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1688 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1689 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1692 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1696 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1709 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1713 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1714 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1717 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1721 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1771 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1778 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1840 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1855 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1933 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1948 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2041 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2049 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2053 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2099 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2103 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2151 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2156 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2161 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2166 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2171 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2176 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2181 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2184 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2187 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2190 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2204 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2205 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2206 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2207 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2209 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2210 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2211 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2212 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2704 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2709 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
3876 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
3878 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;