Lines Matching refs:DestReg
664 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
666 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
670 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
675 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
685 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
687 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
691 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
705 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
709 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
714 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
718 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
722 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
726 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
730 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
735 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
740 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
753 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
761 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); in copyPhysReg()
778 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
988 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
1006 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1010 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1017 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1024 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1025 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1034 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1035 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1038 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1039 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1046 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1050 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1060 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1068 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1069 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1070 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1071 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1072 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1080 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1088 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1089 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1090 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1091 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1092 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1093 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1104 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1105 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1106 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1107 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1108 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1109 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1110 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1111 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1112 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1113 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1292 unsigned DestReg, unsigned SubIdx, in reMaterialize() argument
1299 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1309 DestReg) in reMaterialize()
1755 unsigned DestReg = MI->getOperand(0).getReg(); in optimizeSelect() local
1757 if (!MRI.constrainRegClass(DestReg, PreviousClass)) in optimizeSelect()
1763 DefMI->getDesc(), DestReg); in optimizeSelect()
1842 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitARMRegPlusImmediate() argument
1845 if (NumBytes == 0 && DestReg != BaseReg) { in emitARMRegPlusImmediate()
1846 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
1868 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitARMRegPlusImmediate()
1872 BaseReg = DestReg; in emitARMRegPlusImmediate()