Lines Matching refs:MI
79 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
87 void emitInstruction(const MachineInstr &MI);
93 void emitConstPoolInstruction(const MachineInstr &MI);
94 void emitMOVi32immInstruction(const MachineInstr &MI);
95 void emitMOVi2piecesInstruction(const MachineInstr &MI);
96 void emitLEApcrelJTInstruction(const MachineInstr &MI);
97 void emitPseudoMoveInstruction(const MachineInstr &MI);
99 void emitPseudoInstruction(const MachineInstr &MI);
100 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
106 unsigned getAddrModeSBit(const MachineInstr &MI,
109 void emitDataProcessingInstruction(const MachineInstr &MI,
113 void emitLoadStoreInstruction(const MachineInstr &MI,
117 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
120 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
122 void emitMulFrmInstruction(const MachineInstr &MI);
124 void emitExtendInstruction(const MachineInstr &MI);
126 void emitMiscArithInstruction(const MachineInstr &MI);
128 void emitSaturateInstruction(const MachineInstr &MI);
130 void emitBranchInstruction(const MachineInstr &MI);
134 void emitMiscBranchInstruction(const MachineInstr &MI);
136 void emitVFPArithInstruction(const MachineInstr &MI);
138 void emitVFPConversionInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
142 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
144 void emitNEONLaneInstruction(const MachineInstr &MI);
145 void emitNEONDupInstruction(const MachineInstr &MI);
146 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
147 void emitNEON2RegInstruction(const MachineInstr &MI);
148 void emitNEON3RegInstruction(const MachineInstr &MI);
152 unsigned getMachineOpValue(const MachineInstr &MI,
154 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { in getMachineOpValue() argument
155 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue()
166 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) in NEONThumb2DataIPostEncoder() argument
168 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) in NEONThumb2LoadStorePostEncoder() argument
170 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) in NEONThumb2DupPostEncoder() argument
172 unsigned NEONThumb2V8PostEncoder(const MachineInstr &MI,unsigned Val) in NEONThumb2V8PostEncoder() argument
174 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) in VFPThumb2PostEncoder() argument
176 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) in getAdrLabelOpValue() argument
178 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) in getThumbAdrLabelOpValue() argument
180 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op) in getThumbBLTargetOpValue() argument
182 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) in getThumbBLXTargetOpValue() argument
184 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) in getThumbBRTargetOpValue() argument
186 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) in getThumbBCCTargetOpValue() argument
188 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) in getThumbCBTargetOpValue() argument
190 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) in getBranchTargetOpValue() argument
192 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI, in getUnconditionalBranchTargetOpValue() argument
194 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op) in getARMBranchTargetOpValue() argument
196 unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op) in getARMBLTargetOpValue() argument
198 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op) in getARMBLXTargetOpValue() argument
200 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) in getCCOutOpValue() argument
202 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) in getSOImmOpValue() argument
204 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) in getT2SOImmOpValue() argument
206 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op) in getSORegRegOpValue() argument
208 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op) in getSORegImmOpValue() argument
210 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op) in getThumbAddrModeRegRegOpValue() argument
212 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) in getT2AddrModeImm8OpValue() argument
214 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op) in getT2Imm8s4OpValue() argument
216 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) in getT2AddrModeImm8s4OpValue() argument
218 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op) in getT2AddrModeImm0_1020s4OpValue() argument
220 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) in getT2AddrModeImm8OffsetOpValue() argument
222 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) in getT2AddrModeSORegOpValue() argument
224 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) in getT2SORegOpValue() argument
226 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) in getT2AdrLabelOpValue() argument
228 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) in getAddrMode6AddressOpValue() argument
230 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI, in getAddrMode6OneLane32AddressOpValue() argument
233 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) in getAddrMode6DupAddressOpValue() argument
235 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) in getAddrMode6OffsetOpValue() argument
237 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, in getBitfieldInvertedMaskOpValue() argument
239 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) in getLdStSORegOpValue() argument
242 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) in getAddrModeImm12OpValue() argument
247 const MachineOperand &MO = MI.getOperand(Op); in getAddrModeImm12OpValue()
248 const MachineOperand &MO1 = MI.getOperand(Op + 1); in getAddrModeImm12OpValue()
263 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const { in getHiLo16ImmOpValue() argument
267 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode2OffsetOpValue() argument
269 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) in getPostIdxRegOpValue() argument
271 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode3OffsetOpValue() argument
273 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) in getAddrMode3OpValue() argument
275 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op) in getAddrModeThumbSPOpValue() argument
277 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op) in getAddrModeISOpValue() argument
279 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) in getAddrModePCOpValue() argument
281 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { in getAddrMode5OpValue() argument
285 const MachineOperand &MO = MI.getOperand(Op); in getAddrMode5OpValue()
286 const MachineOperand &MO1 = MI.getOperand(Op + 1); in getAddrMode5OpValue()
312 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) in getNEONVcvtImm32OpValue() argument
315 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) in getRegisterListOpValue() argument
318 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op) in getShiftRight8Imm() argument
320 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op) in getShiftRight16Imm() argument
322 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op) in getShiftRight32Imm() argument
324 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op) in getShiftRight64Imm() argument
330 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
347 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
348 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
349 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const;
350 unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const;
351 unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const;
352 unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const;
417 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, in getMovi32Value() argument
442 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, in getMachineOpValue() argument
453 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue()
529 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { in emitInstruction() argument
530 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); in emitInstruction()
532 MCE.processDebugLoc(MI.getDebugLoc(), true); in emitInstruction()
535 switch (MI.getDesc().TSFlags & ARMII::FormMask) { in emitInstruction()
540 if (MI.getOpcode() == ARM::LEApcrelJT) { in emitInstruction()
542 emitLEApcrelJTInstruction(MI); in emitInstruction()
547 emitPseudoInstruction(MI); in emitInstruction()
551 emitDataProcessingInstruction(MI); in emitInstruction()
555 emitLoadStoreInstruction(MI); in emitInstruction()
559 emitMiscLoadStoreInstruction(MI); in emitInstruction()
562 emitLoadStoreMultipleInstruction(MI); in emitInstruction()
565 emitMulFrmInstruction(MI); in emitInstruction()
568 emitExtendInstruction(MI); in emitInstruction()
571 emitMiscArithInstruction(MI); in emitInstruction()
574 emitSaturateInstruction(MI); in emitInstruction()
577 emitBranchInstruction(MI); in emitInstruction()
580 emitMiscBranchInstruction(MI); in emitInstruction()
585 emitVFPArithInstruction(MI); in emitInstruction()
592 emitVFPConversionInstruction(MI); in emitInstruction()
595 emitVFPLoadStoreInstruction(MI); in emitInstruction()
598 emitVFPLoadStoreMultipleInstruction(MI); in emitInstruction()
604 emitNEONLaneInstruction(MI); in emitInstruction()
607 emitNEONDupInstruction(MI); in emitInstruction()
610 emitNEON1RegModImmInstruction(MI); in emitInstruction()
613 emitNEON2RegInstruction(MI); in emitInstruction()
616 emitNEON3RegInstruction(MI); in emitInstruction()
619 MCE.processDebugLoc(MI.getDebugLoc(), false); in emitInstruction()
622 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { in emitConstPoolInstruction() argument
623 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. in emitConstPoolInstruction()
624 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. in emitConstPoolInstruction()
685 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { in emitMOVi32immInstruction() argument
686 const MachineOperand &MO0 = MI.getOperand(0); in emitMOVi32immInstruction()
687 const MachineOperand &MO1 = MI.getOperand(1); in emitMOVi32immInstruction()
692 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; in emitMOVi32immInstruction()
695 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitMOVi32immInstruction()
698 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi32immInstruction()
705 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; in emitMOVi32immInstruction()
710 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitMOVi32immInstruction()
713 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi32immInstruction()
721 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { in emitMOVi2piecesInstruction() argument
722 const MachineOperand &MO0 = MI.getOperand(0); in emitMOVi2piecesInstruction()
723 const MachineOperand &MO1 = MI.getOperand(1); in emitMOVi2piecesInstruction()
733 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitMOVi2piecesInstruction()
736 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi2piecesInstruction()
748 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitMOVi2piecesInstruction()
751 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi2piecesInstruction()
754 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; in emitMOVi2piecesInstruction()
763 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { in emitLEApcrelJTInstruction() argument
766 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction()
772 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitLEApcrelJTInstruction()
775 Binary |= getAddrModeSBit(MI, MCID); in emitLEApcrelJTInstruction()
778 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; in emitLEApcrelJTInstruction()
785 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); in emitLEApcrelJTInstruction()
790 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { in emitPseudoMoveInstruction() argument
791 unsigned Opcode = MI.getDesc().Opcode; in emitPseudoMoveInstruction()
794 unsigned Binary = getBinaryCodeForInstr(MI); in emitPseudoMoveInstruction()
797 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitPseudoMoveInstruction()
804 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; in emitPseudoMoveInstruction()
824 Binary |= getMachineOpValue(MI, 1); in emitPseudoMoveInstruction()
835 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { in emitPseudoInstruction() argument
836 unsigned Opcode = MI.getDesc().Opcode; in emitPseudoInstruction()
844 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitPseudoInstruction()
848 emitMiscBranchInstruction(MI); in emitPseudoInstruction()
854 if (MI.getOperand(0).getSymbolName()[0]) { in emitPseudoInstruction()
862 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); in emitPseudoInstruction()
869 emitConstPoolInstruction(MI); in emitPseudoInstruction()
873 addPCLabel(MI.getOperand(2).getImm()); in emitPseudoInstruction()
875 emitDataProcessingInstruction(MI, 0, ARM::PC); in emitPseudoInstruction()
883 addPCLabel(MI.getOperand(2).getImm()); in emitPseudoInstruction()
885 emitLoadStoreInstruction(MI, 0, ARM::PC); in emitPseudoInstruction()
893 addPCLabel(MI.getOperand(2).getImm()); in emitPseudoInstruction()
895 emitMiscLoadStoreInstruction(MI, ARM::PC); in emitPseudoInstruction()
902 emitMOVi32immInstruction(MI); in emitPseudoInstruction()
904 emitMOVi2piecesInstruction(MI); in emitPseudoInstruction()
909 emitLEApcrelJTInstruction(MI); in emitPseudoInstruction()
914 emitPseudoMoveInstruction(MI); in emitPseudoInstruction()
919 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, in getMachineSoRegOpValue() argument
923 unsigned Binary = getMachineOpValue(MI, MO); in getMachineSoRegOpValue()
925 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); in getMachineSoRegOpValue()
926 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); in getMachineSoRegOpValue()
989 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, in getAddrModeSBit() argument
991 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){ in getAddrModeSBit()
992 const MachineOperand &MO = MI.getOperand(i-1); in getAddrModeSBit()
999 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, in emitDataProcessingInstruction() argument
1002 const MCInstrDesc &MCID = MI.getDesc(); in emitDataProcessingInstruction()
1005 unsigned Binary = getBinaryCodeForInstr(MI); in emitDataProcessingInstruction()
1008 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitDataProcessingInstruction()
1011 Binary |= getAddrModeSBit(MI, MCID); in emitDataProcessingInstruction()
1017 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitDataProcessingInstruction()
1024 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), in emitDataProcessingInstruction()
1032 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), in emitDataProcessingInstruction()
1039 uint32_t v = ~MI.getOperand(2).getImm(); in emitDataProcessingInstruction()
1049 Binary |= getMachineOpValue(MI, OpIdx++); in emitDataProcessingInstruction()
1051 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); in emitDataProcessingInstruction()
1052 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; in emitDataProcessingInstruction()
1072 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; in emitDataProcessingInstruction()
1078 const MachineOperand &MO = MI.getOperand(OpIdx); in emitDataProcessingInstruction()
1081 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx)); in emitDataProcessingInstruction()
1097 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, in emitLoadStoreInstruction() argument
1100 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreInstruction()
1105 unsigned Binary = getBinaryCodeForInstr(MI); in emitLoadStoreInstruction()
1108 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || in emitLoadStoreInstruction()
1109 MI.getOpcode() == ARM::STRi12) { in emitLoadStoreInstruction()
1115 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitLoadStoreInstruction()
1132 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitLoadStoreInstruction()
1139 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; in emitLoadStoreInstruction()
1145 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitLoadStoreInstruction()
1147 ? 0 : MI.getOperand(OpIdx+1).getImm(); in emitLoadStoreInstruction()
1176 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, in emitMiscLoadStoreInstruction() argument
1178 const MCInstrDesc &MCID = MI.getDesc(); in emitMiscLoadStoreInstruction()
1183 unsigned Binary = getBinaryCodeForInstr(MI); in emitMiscLoadStoreInstruction()
1186 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitMiscLoadStoreInstruction()
1199 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitMiscLoadStoreInstruction()
1210 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; in emitMiscLoadStoreInstruction()
1216 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitMiscLoadStoreInstruction()
1218 ? 0 : MI.getOperand(OpIdx+1).getImm(); in emitMiscLoadStoreInstruction()
1262 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { in emitLoadStoreMultipleInstruction() argument
1263 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreMultipleInstruction()
1267 unsigned Binary = getBinaryCodeForInstr(MI); in emitLoadStoreMultipleInstruction()
1270 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitLoadStoreMultipleInstruction()
1278 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; in emitLoadStoreMultipleInstruction()
1281 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); in emitLoadStoreMultipleInstruction()
1289 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { in emitLoadStoreMultipleInstruction()
1290 const MachineOperand &MO = MI.getOperand(i); in emitLoadStoreMultipleInstruction()
1302 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { in emitMulFrmInstruction() argument
1303 const MCInstrDesc &MCID = MI.getDesc(); in emitMulFrmInstruction()
1306 unsigned Binary = getBinaryCodeForInstr(MI); in emitMulFrmInstruction()
1309 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitMulFrmInstruction()
1312 Binary |= getAddrModeSBit(MI, MCID); in emitMulFrmInstruction()
1318 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; in emitMulFrmInstruction()
1321 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; in emitMulFrmInstruction()
1324 Binary |= getMachineOpValue(MI, OpIdx++); in emitMulFrmInstruction()
1327 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; in emitMulFrmInstruction()
1334 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; in emitMulFrmInstruction()
1339 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { in emitExtendInstruction() argument
1340 const MCInstrDesc &MCID = MI.getDesc(); in emitExtendInstruction()
1343 unsigned Binary = getBinaryCodeForInstr(MI); in emitExtendInstruction()
1346 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitExtendInstruction()
1351 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitExtendInstruction()
1353 const MachineOperand &MO1 = MI.getOperand(OpIdx++); in emitExtendInstruction()
1354 const MachineOperand &MO2 = MI.getOperand(OpIdx); in emitExtendInstruction()
1358 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; in emitExtendInstruction()
1361 Binary |= getMachineOpValue(MI, MO2); in emitExtendInstruction()
1364 Binary |= getMachineOpValue(MI, MO1); in emitExtendInstruction()
1368 if (MI.getOperand(OpIdx).isImm() && in emitExtendInstruction()
1371 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; in emitExtendInstruction()
1376 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { in emitMiscArithInstruction() argument
1377 const MCInstrDesc &MCID = MI.getDesc(); in emitMiscArithInstruction()
1380 unsigned Binary = getBinaryCodeForInstr(MI); in emitMiscArithInstruction()
1383 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitMiscArithInstruction()
1394 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; in emitMiscArithInstruction()
1396 const MachineOperand &MO = MI.getOperand(OpIdx++); in emitMiscArithInstruction()
1401 Binary |= getMachineOpValue(MI, MO); in emitMiscArithInstruction()
1407 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; in emitMiscArithInstruction()
1410 Binary |= getMachineOpValue(MI, OpIdx++); in emitMiscArithInstruction()
1413 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); in emitMiscArithInstruction()
1425 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { in emitSaturateInstruction() argument
1426 const MCInstrDesc &MCID = MI.getDesc(); in emitSaturateInstruction()
1429 unsigned Binary = getBinaryCodeForInstr(MI); in emitSaturateInstruction()
1432 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitSaturateInstruction()
1435 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; in emitSaturateInstruction()
1438 unsigned Pos = MI.getOperand(1).getImm(); in emitSaturateInstruction()
1448 Binary |= getMachineOpValue(MI, 2); in emitSaturateInstruction()
1452 unsigned ShiftOp = MI.getOperand(3).getImm(); in emitSaturateInstruction()
1456 unsigned ShiftAmt = MI.getOperand(3).getImm(); in emitSaturateInstruction()
1466 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { in emitBranchInstruction() argument
1467 const MCInstrDesc &MCID = MI.getDesc(); in emitBranchInstruction()
1474 unsigned Binary = getBinaryCodeForInstr(MI); in emitBranchInstruction()
1477 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitBranchInstruction()
1480 Binary |= getMachineOpValue(MI, 0); in emitBranchInstruction()
1505 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { in emitMiscBranchInstruction() argument
1506 const MCInstrDesc &MCID = MI.getDesc(); in emitMiscBranchInstruction()
1511 emitDataProcessingInstruction(MI, ARM::PC); in emitMiscBranchInstruction()
1516 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); in emitMiscBranchInstruction()
1521 emitLoadStoreInstruction(MI, ARM::PC); in emitMiscBranchInstruction()
1524 emitInlineJumpTable(MI.getOperand(3).getIndex()); in emitMiscBranchInstruction()
1529 unsigned Binary = getBinaryCodeForInstr(MI); in emitMiscBranchInstruction()
1532 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitMiscBranchInstruction()
1539 Binary |= getMachineOpValue(MI, 0); in emitMiscBranchInstruction()
1544 unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI, in encodeVFPRd() argument
1546 unsigned RegD = MI.getOperand(OpIdx).getReg(); in encodeVFPRd()
1559 unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI, in encodeVFPRn() argument
1561 unsigned RegN = MI.getOperand(OpIdx).getReg(); in encodeVFPRn()
1574 unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI, in encodeVFPRm() argument
1576 unsigned RegM = MI.getOperand(OpIdx).getReg(); in encodeVFPRm()
1589 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { in emitVFPArithInstruction() argument
1590 const MCInstrDesc &MCID = MI.getDesc(); in emitVFPArithInstruction()
1593 unsigned Binary = getBinaryCodeForInstr(MI); in emitVFPArithInstruction()
1596 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitVFPArithInstruction()
1604 Binary |= encodeVFPRd(MI, OpIdx++); in emitVFPArithInstruction()
1612 Binary |= encodeVFPRn(MI, OpIdx++); in emitVFPArithInstruction()
1623 Binary |= encodeVFPRm(MI, OpIdx); in emitVFPArithInstruction()
1628 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { in emitVFPConversionInstruction() argument
1629 const MCInstrDesc &MCID = MI.getDesc(); in emitVFPConversionInstruction()
1633 unsigned Binary = getBinaryCodeForInstr(MI); in emitVFPConversionInstruction()
1636 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitVFPConversionInstruction()
1644 Binary |= encodeVFPRd(MI, 0); in emitVFPConversionInstruction()
1648 Binary |= encodeVFPRn(MI, 0); in emitVFPConversionInstruction()
1652 Binary |= encodeVFPRm(MI, 0); in emitVFPConversionInstruction()
1660 Binary |= encodeVFPRm(MI, 1); in emitVFPConversionInstruction()
1665 Binary |= encodeVFPRn(MI, 1); in emitVFPConversionInstruction()
1670 Binary |= encodeVFPRd(MI, 1); in emitVFPConversionInstruction()
1676 Binary |= encodeVFPRn(MI, 2); in emitVFPConversionInstruction()
1679 Binary |= encodeVFPRm(MI, 2); in emitVFPConversionInstruction()
1684 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { in emitVFPLoadStoreInstruction() argument
1686 unsigned Binary = getBinaryCodeForInstr(MI); in emitVFPLoadStoreInstruction()
1689 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitVFPLoadStoreInstruction()
1694 Binary |= encodeVFPRd(MI, OpIdx++); in emitVFPLoadStoreInstruction()
1697 const MachineOperand &Base = MI.getOperand(OpIdx++); in emitVFPLoadStoreInstruction()
1698 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; in emitVFPLoadStoreInstruction()
1702 const MachineOperand &Offset = MI.getOperand(OpIdx); in emitVFPLoadStoreInstruction()
1719 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { in emitVFPLoadStoreMultipleInstruction() argument
1720 const MCInstrDesc &MCID = MI.getDesc(); in emitVFPLoadStoreMultipleInstruction()
1724 unsigned Binary = getBinaryCodeForInstr(MI); in emitVFPLoadStoreMultipleInstruction()
1727 Binary |= II->getPredicate(&MI) << ARMII::CondShift; in emitVFPLoadStoreMultipleInstruction()
1735 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; in emitVFPLoadStoreMultipleInstruction()
1738 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); in emitVFPLoadStoreMultipleInstruction()
1746 Binary |= encodeVFPRd(MI, OpIdx+2); in emitVFPLoadStoreMultipleInstruction()
1750 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { in emitVFPLoadStoreMultipleInstruction()
1751 const MachineOperand &MO = MI.getOperand(i); in emitVFPLoadStoreMultipleInstruction()
1766 unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI, in encodeNEONRd() argument
1768 unsigned RegD = MI.getOperand(OpIdx).getReg(); in encodeNEONRd()
1776 unsigned ARMCodeEmitter::encodeNEONRn(const MachineInstr &MI, in encodeNEONRn() argument
1778 unsigned RegN = MI.getOperand(OpIdx).getReg(); in encodeNEONRn()
1786 unsigned ARMCodeEmitter::encodeNEONRm(const MachineInstr &MI, in encodeNEONRm() argument
1788 unsigned RegM = MI.getOperand(OpIdx).getReg(); in encodeNEONRm()
1805 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { in emitNEONLaneInstruction() argument
1806 unsigned Binary = getBinaryCodeForInstr(MI); in emitNEONLaneInstruction()
1809 const MCInstrDesc &MCID = MI.getDesc(); in emitNEONLaneInstruction()
1821 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; in emitNEONLaneInstruction()
1823 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); in emitNEONLaneInstruction()
1826 Binary |= encodeNEONRn(MI, RegNOpIdx); in emitNEONLaneInstruction()
1836 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; in emitNEONLaneInstruction()
1846 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { in emitNEONDupInstruction() argument
1847 unsigned Binary = getBinaryCodeForInstr(MI); in emitNEONDupInstruction()
1850 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; in emitNEONDupInstruction()
1852 unsigned RegT = MI.getOperand(1).getReg(); in emitNEONDupInstruction()
1855 Binary |= encodeNEONRn(MI, 0); in emitNEONDupInstruction()
1859 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { in emitNEON1RegModImmInstruction() argument
1860 unsigned Binary = getBinaryCodeForInstr(MI); in emitNEON1RegModImmInstruction()
1862 Binary |= encodeNEONRd(MI, 0); in emitNEON1RegModImmInstruction()
1864 unsigned Imm = MI.getOperand(1).getImm(); in emitNEON1RegModImmInstruction()
1876 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { in emitNEON2RegInstruction() argument
1877 const MCInstrDesc &MCID = MI.getDesc(); in emitNEON2RegInstruction()
1878 unsigned Binary = getBinaryCodeForInstr(MI); in emitNEON2RegInstruction()
1881 Binary |= encodeNEONRd(MI, OpIdx++); in emitNEON2RegInstruction()
1884 Binary |= encodeNEONRm(MI, OpIdx); in emitNEON2RegInstruction()
1891 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { in emitNEON3RegInstruction() argument
1892 const MCInstrDesc &MCID = MI.getDesc(); in emitNEON3RegInstruction()
1893 unsigned Binary = getBinaryCodeForInstr(MI); in emitNEON3RegInstruction()
1896 Binary |= encodeNEONRd(MI, OpIdx++); in emitNEON3RegInstruction()
1899 Binary |= encodeNEONRn(MI, OpIdx++); in emitNEON3RegInstruction()
1902 Binary |= encodeNEONRm(MI, OpIdx); in emitNEON3RegInstruction()